[PATCH] D144271: [AMDGPU][MC] Enable modifiers on V_MOV_B32

Tue Feb 21 00:57:55 PST 2023

foad added a comment.

In D144271#4139988 <https://reviews.llvm.org/D144271#4139988>, @Joe_Nash wrote:

> In D144271#4139981 <https://reviews.llvm.org/D144271#4139981>, @arsenm wrote:
>
>> In D144271#4139979 <https://reviews.llvm.org/D144271#4139979>, @Joe_Nash wrote:
>>
>>> Actually, I think due to the way the operand lists for _e32 instructions are constructed, the modifiers are not taking effect.
>>> If you dump the tablegen records, if the change was effective there should be a src0_modifiers operand on the V_MOV_B32_e32 instruction.
>>
>> I'd expect it to only be on v_mov_b32_e64?
>
> I guess the spec was changed between gfx9 and gfx10. On gfx10 and newer the docs say modifiers are supported on VOP1 as well as VOP3. But in terms of what our backend would make with just the above patch, it seems the modifiers would be on v_mov_b32_e64 but not v_mov_b32_e32. Hence my ask to check the tablegen records.

There are no modifiers in VOP1 - there are no bits in the encoding for them.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144271/new/

https://reviews.llvm.org/D144271