[PATCH] D143646: [RISCV] Return false from shouldFormOverflowOp

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:8923
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  if (OpVT == MVT::i64 && !Subtarget.is64Bit() && Cond == ISD::SETULT &&
+      N0->getOpcode() == ISD::ADD && !isa<ConstantSDNode>(N1) &&
----------------
I don't understand this criteria. Just looking at the operands of the add is arbitrary. In your example, it seems like the select is important, but you don't check for that.


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  https://reviews.llvm.org/D143646/new/

https://reviews.llvm.org/D143646