[llvm] 7f31a5c - [RISCV] Add fgtq.s and fgeq.s assembler aliases for Zfa.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-02-19T12:28:01-08:00
New Revision: 7f31a5c4c647ecdca010072f547f30f77ed1ab3e

URL: https://github.com/llvm/llvm-project/commit/7f31a5c4c647ecdca010072f547f30f77ed1ab3e
DIFF: https://github.com/llvm/llvm-project/commit/7f31a5c4c647ecdca010072f547f30f77ed1ab3e.diff

LOG: [RISCV] Add fgtq.s and fgeq.s assembler aliases for Zfa.

We can swap operands and use fltq.s and fleq.s. Similar for D and H.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    llvm/test/MC/RISCV/zfa-valid.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index eb719a19e80d0..845718f8a1d4e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -102,6 +102,30 @@ def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16>;
 def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+//===----------------------------------------------------------------------===//
+// Pseudo-instructions and codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZfa] in {
+def : InstAlias<"fgtq.s $rd, $rs, $rt",
+                (FLTQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
+def : InstAlias<"fgeq.s $rd, $rs, $rt",
+                (FLEQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
+}
+
+let Predicates = [HasStdExtZfa, HasStdExtD] in {
+def : InstAlias<"fgtq.d $rd, $rs, $rt",
+                (FLTQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
+def : InstAlias<"fgeq.d $rd, $rs, $rt",
+                (FLEQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
+}
+
+let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
+def : InstAlias<"fgtq.h $rd, $rs, $rt",
+                (FLTQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
+def : InstAlias<"fgeq.h $rd, $rs, $rt",
+                (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
+}
 
 //===----------------------------------------------------------------------===//
 // Codegen patterns

diff  --git a/llvm/test/MC/RISCV/zfa-valid.s b/llvm/test/MC/RISCV/zfa-valid.s
index d67fc81bc35a0..0d307fc527b57 100644
--- a/llvm/test/MC/RISCV/zfa-valid.s
+++ b/llvm/test/MC/RISCV/zfa-valid.s
@@ -176,10 +176,20 @@ fcvtmod.w.d a1, ft1, rtz
 # CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
 fltq.s a1, fs1, fs2
 
-# CHECK-ASM-AND-OBJ: fleq.s a1, ft1, ft1
-# CHECK-ASM: encoding: [0xd3,0xc5,0x10,0xa0]
+# CHECK-ASM-AND-OBJ: fleq.s a1, ft1, ft2
+# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa0]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
-fleq.s a1, ft1, ft1
+fleq.s a1, ft1, ft2
+
+# CHECK-ASM-AND-OBJ: fltq.s a1, fs2, fs1
+# CHECK-ASM: encoding: [0xd3,0x55,0x99,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fgtq.s a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.s a1, ft2, ft1
+# CHECK-ASM: encoding: [0xd3,0x45,0x11,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fgeq.s a1, ft1, ft2
 
 # CHECK-ASM-AND-OBJ: fltq.d a1, fs1, fs2
 # CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa3]
@@ -191,6 +201,16 @@ fltq.d a1, fs1, fs2
 # CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
 fleq.d a1, ft1, ft2
 
+# CHECK-ASM-AND-OBJ: fltq.d a1, fs2, fs1
+# CHECK-ASM: encoding: [0xd3,0x55,0x99,0xa2]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fgtq.d a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.d a1, ft2, ft1
+# CHECK-ASM: encoding: [0xd3,0x45,0x11,0xa2]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fgeq.d a1, ft1, ft2
+
 # CHECK-ASM-AND-OBJ: fltq.h a1, fs1, fs2
 # CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa5]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
@@ -200,3 +220,13 @@ fltq.h a1, fs1, fs2
 # CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa4]
 # CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
 fleq.h a1, ft1, ft2
+
+# CHECK-ASM-AND-OBJ: fltq.h a1, fs2, fs1
+# CHECK-ASM: encoding: [0xd3,0x55,0x99,0xa4]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fgtq.h a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.h a1, ft2, ft1
+# CHECK-ASM: encoding: [0xd3,0x45,0x11,0xa4]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fgeq.h a1, ft1, ft2