[llvm] 78f106a - [RISCV] Handle RISCVISD::SplitF64 and RISCVISD::BuildPairF64 during isel with Zfa.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-02-18T17:03:55-08:00
New Revision: 78f106a554b0c3ee8468ce291b5df5a730207490

URL: https://github.com/llvm/llvm-project/commit/78f106a554b0c3ee8468ce291b5df5a730207490
DIFF: https://github.com/llvm/llvm-project/commit/78f106a554b0c3ee8468ce291b5df5a730207490.diff

LOG: [RISCV] Handle RISCVISD::SplitF64 and RISCVISD::BuildPairF64 during isel with Zfa.

Instead of special casing Zfa in the custom inserters, select the
correct instructions during isel.

BuildPairF64 we can do with pattern, but SplitF64 requires custom
selection due to the two destinations.

If we didn't need SplitF64 without Zfa, I would have an extract low
and extract high ISD opcode for Zfa to avoid that issue.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 4a7ba8bee410b..2c2d7d306b944 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -809,6 +809,27 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     ReplaceNode(Node, Res);
     return;
   }
+  case RISCVISD::SplitF64: {
+    if (!Subtarget->hasStdExtZfa())
+      break;
+    assert(Subtarget->hasStdExtD() && !Subtarget->is64Bit() &&
+           "Unexpected subtarget");
+
+    // With Zfa, lower to fmv.x.w and fmvh.x.d.
+    if (!SDValue(Node, 0).use_empty()) {
+      SDNode *Lo = CurDAG->getMachineNode(RISCV::FMV_X_W_FPR64, DL, VT,
+                                          Node->getOperand(0));
+      ReplaceUses(SDValue(Node, 0), SDValue(Lo, 0));
+    }
+    if (!SDValue(Node, 1).use_empty()) {
+      SDNode *Hi = CurDAG->getMachineNode(RISCV::FMVH_X_D, DL, VT,
+                                          Node->getOperand(0));
+      ReplaceUses(SDValue(Node, 1), SDValue(Hi, 0));
+    }
+
+    CurDAG->RemoveDeadNode(Node);
+    return;
+  }
   case ISD::SHL: {
     auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
     if (!N1C)

diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0f00fc85068bb..e5734e13f7af8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11188,13 +11188,6 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
   Register LoReg = MI.getOperand(0).getReg();
   Register HiReg = MI.getOperand(1).getReg();
   Register SrcReg = MI.getOperand(2).getReg();
-  if (Subtarget.hasStdExtD() && Subtarget.hasStdExtZfa() &&
-      !Subtarget.is64Bit()) {
-    BuildMI(*BB, MI, DL, TII.get(RISCV::FMV_X_W_FPR64), LoReg).addReg(SrcReg);
-    BuildMI(*BB, MI, DL, TII.get(RISCV::FMVH_X_D), HiReg).addReg(SrcReg);
-    MI.eraseFromParent(); // The pseudo instruction is gone now.
-    return BB;
-  }
 
   const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
   int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
@@ -11231,14 +11224,6 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
   Register DstReg = MI.getOperand(0).getReg();
   Register LoReg = MI.getOperand(1).getReg();
   Register HiReg = MI.getOperand(2).getReg();
-  if (Subtarget.hasStdExtD() && Subtarget.hasStdExtZfa() &&
-      !Subtarget.is64Bit()) {
-    BuildMI(*BB, MI, DL, TII.get(RISCV::FMVP_D_X), DstReg)
-        .addReg(LoReg)
-        .addReg(HiReg);
-    MI.eraseFromParent();
-    return BB;
-  }
 
   const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
   int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 609a8662ff8f3..586df6b5df0fd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -152,6 +152,11 @@ def: PatSetCC<FPR64, strict_fsetcc, SETLE, FLEQ_D>;
 def: PatSetCC<FPR64, strict_fsetcc, SETOLE, FLEQ_D>;
 } // Predicates = [HasStdExtZfa, HasStdExtD]
 
+let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
+def : Pat<(RISCVBuildPairF64 GPR:$rs1, GPR:$rs2),
+          (FMVP_D_X GPR:$rs1, GPR:$rs2)>;
+}
+
 let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
 def: PatFprFpr<fminimum, FMINM_H, FPR16>;
 def: PatFprFpr<fmaximum, FMAXM_H, FPR16>;