[PATCH] D144175: [RISCV] Combine (store/load interleave, deinterleave) into vsseg2/vlseg2

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10873
+    if (auto *Interleave = getVectorInterleaveFromStore(Store)) {
+      if (!Val.getValueType().isSimple())
+        break;
----------------
I don't think check simple is enough. You need to check isTypeLegal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144175/new/

https://reviews.llvm.org/D144175