[llvm] a883163 - [InstCombine] add tests for 1<<cttz(x); NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2023-02-18T08:34:55-05:00
New Revision: a8831631c7ec74f91c12963e45b062c3366dd10d

URL: https://github.com/llvm/llvm-project/commit/a8831631c7ec74f91c12963e45b062c3366dd10d
DIFF: https://github.com/llvm/llvm-project/commit/a8831631c7ec74f91c12963e45b062c3366dd10d.diff

LOG: [InstCombine] add tests for 1<<cttz(x); NFC

issue #60799
issue #60801

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/shift.ll

Removed: 
    


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diff  --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index 710ae117bae01..8d2e4d97bad28 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -1,6 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
+declare void @use(i64)
+declare void @use_i32(i32)
+
+declare i32 @llvm.cttz.i32(i32, i1 immarg)
+declare <2 x i8> @llvm.cttz.v2i8(<2 x i8>, i1 immarg)
+
 define <4 x i32> @lshr_non_splat_vector(<4 x i32> %A) {
 ; CHECK-LABEL: @lshr_non_splat_vector(
 ; CHECK-NEXT:    [[B:%.*]] = lshr <4 x i32> [[A:%.*]], <i32 32, i32 1, i32 2, i32 3>
@@ -110,8 +116,8 @@ define i8 @test11a(i8 %A) {
 ;; (A >> 8) << 8 === A & -256
 define i32 @test12(i32 %A) {
 ; CHECK-LABEL: @test12(
-; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], -256
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[C:%.*]] = and i32 [[A:%.*]], -256
+; CHECK-NEXT:    ret i32 [[C]]
 ;
   %B = ashr i32 %A, 8
   %C = shl i32 %B, 8
@@ -357,7 +363,6 @@ define i32 @test26(i32 %A) {
   ret i32 %D
 }
 
-
 define i1 @test27(i32 %x) nounwind {
 ; CHECK-LABEL: @test27(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[X:%.*]], 8
@@ -1247,8 +1252,6 @@ define i64 @shl_zext(i32 %t) {
   ret i64 %shl
 }
 
-declare void @use(i64)
-
 define i64 @shl_zext_extra_use(i32 %t) {
 ; CHECK-LABEL: @shl_zext_extra_use(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[T:%.*]], 16777215
@@ -1264,7 +1267,6 @@ define i64 @shl_zext_extra_use(i32 %t) {
   ret i64 %shl
 }
 
-
 define <2 x i64> @shl_zext_splat_vec(<2 x i32> %t) {
 ; CHECK-LABEL: @shl_zext_splat_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> [[T:%.*]], <i32 8, i32 8>
@@ -1331,8 +1333,6 @@ define i64 @shl_zext_mul_extra_use1(i32 %t) {
   ret i64 %shl
 }
 
-declare void @use_i32(i32)
-
 define i64 @shl_zext_mul_extra_use2(i32 %t) {
 ; CHECK-LABEL: @shl_zext_mul_extra_use2(
 ; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[T:%.*]], 16777215
@@ -2006,3 +2006,60 @@ define i32 @ashr_sdiv_extra_use(i32 %x) {
   %r = ashr i32 %d, 31
   ret i32 %r
 }
+
+define i32 @shl1_cttz(i32 %x) {
+; CHECK-LABEL: @shl1_cttz(
+; CHECK-NEXT:    [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i32 1, [[TZ]]
+; CHECK-NEXT:    ret i32 [[SHL]]
+;
+  %tz = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %shl = shl i32 1, %tz
+  ret i32 %shl
+}
+
+define <2 x i8> @shl1_cttz_vec(<2 x i8> %x) {
+; CHECK-LABEL: @shl1_cttz_vec(
+; CHECK-NEXT:    [[TZ:%.*]] = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw <2 x i8> <i8 1, i8 1>, [[TZ]]
+; CHECK-NEXT:    ret <2 x i8> [[SHL]]
+;
+  %tz = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 false)
+  %shl = shl <2 x i8> <i8 1, i8 1>, %tz
+  ret <2 x i8> %shl
+}
+
+define <2 x i8> @shl1_cttz_vec_poison(<2 x i8> %x) {
+; CHECK-LABEL: @shl1_cttz_vec_poison(
+; CHECK-NEXT:    [[TZ:%.*]] = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw <2 x i8> <i8 1, i8 poison>, [[TZ]]
+; CHECK-NEXT:    ret <2 x i8> [[SHL]]
+;
+  %tz = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %x, i1 false)
+  %shl = shl <2 x i8> <i8 1, i8 poison>, %tz
+  ret <2 x i8> %shl
+}
+
+define i32 @shl1_cttz_extra_use(i32 %x) {
+; CHECK-LABEL: @shl1_cttz_extra_use(
+; CHECK-NEXT:    [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]]
+; CHECK-NEXT:    call void @use_i32(i32 [[TZ]])
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i32 1, [[TZ]]
+; CHECK-NEXT:    ret i32 [[SHL]]
+;
+  %tz = call i32 @llvm.cttz.i32(i32 %x, i1 false)
+  call void @use_i32(i32 %tz)
+  %shl = shl i32 1, %tz
+  ret i32 %shl
+}
+
+define i32 @shl2_cttz(i32 %x) {
+; CHECK-LABEL: @shl2_cttz(
+; CHECK-NEXT:    [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 2, [[TZ]]
+; CHECK-NEXT:    ret i32 [[SHL]]
+;
+  %tz = call i32 @llvm.cttz.i32(i32 %x, i1 true)
+  %shl = shl i32 2, %tz
+  ret i32 %shl
+}