[PATCH] D144324: [AArch64][SelectionDAG] Perfer CMN for (0 - Y) == Y
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 18 00:50:43 PST 2023
Allen updated this revision to Diff 498569.
Allen added a comment.
update comment
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144324/new/
https://reviews.llvm.org/D144324
Files:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
Index: llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
===================================================================
--- llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
+++ llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
@@ -397,3 +397,15 @@
%cmp = icmp ne i32 %conv, %add
ret i1 %cmp
}
+
+define i1 @PR60818(i32 %a) {
+; CHECK-LABEL: PR60818:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmn w0, w0
+; CHECK-NEXT: cset w0, ne
+; CHECK-NEXT: ret
+entry:
+ %sub = sub i32 0, %a
+ %cmp = icmp ne i32 %sub, %a
+ ret i1 %cmp
+}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4011,6 +4011,11 @@
if (!N0.hasOneUse() || OpVT.getScalarSizeInBits() == 1)
return SDValue();
+ // The shift would be disable as we prefer CMN for (0 - Y) == Y
+ if (ConstantSDNode *CTVal = isConstOrConstSplat(X))
+ if (CTVal->isZero())
+ return SDValue();
+
// (X - Y) == Y --> X == Y << 1
EVT ShiftVT = getShiftAmountTy(OpVT, DAG.getDataLayout(),
!DCI.isBeforeLegalize());
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