[llvm] 432caca - Simplify with hasFeature. NFC
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 17 18:22:28 PST 2023
Author: Fangrui Song
Date: 2023-02-17T18:22:24-08:00
New Revision: 432caca39a62f4d20b8f38c139a3a462ea2a7f77
URL: https://github.com/llvm/llvm-project/commit/432caca39a62f4d20b8f38c139a3a462ea2a7f77
DIFF: https://github.com/llvm/llvm-project/commit/432caca39a62f4d20b8f38c139a3a462ea2a7f77.diff
LOG: Simplify with hasFeature. NFC
Added:
Modified:
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 342a8137f6505..e8469c2e41e31 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -51,7 +51,7 @@ AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
// ToDo: AMDGPUDisassembler supports only VI ISA.
- if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus())
+ if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
report_fatal_error("Disassembly not yet supported for subtarget");
}
@@ -456,7 +456,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Bytes.size() >= 8) {
const uint64_t QW = eatBytes<uint64_t>(Bytes);
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
if (Res) {
if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
@@ -497,7 +497,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
if (Res) { IsSDWA = true; break; }
- if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
+ if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
if (Res)
break;
@@ -506,7 +506,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
// Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
// v_mad_mixhi_f16 for FMA variants. Try to decode using this special
// table first so we print the correct name.
- if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
+ if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) {
Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
if (Res)
break;
@@ -528,13 +528,13 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
if (Res) break;
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address);
if (Res)
break;
}
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
if (Res) break;
}
@@ -548,13 +548,13 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Bytes.size() < 4) break;
const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) {
Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address);
if (Res)
break;
}
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address);
if (Res)
break;
@@ -604,7 +604,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (Res && (MCII->get(MI.getOpcode()).TSFlags &
(SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) &&
- (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) {
+ (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) {
// GFX90A lost TFE, its place is occupied by ACC.
int TFEOpIdx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
@@ -691,7 +691,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
}
DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const {
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX11)) {
// The MCInst still has these fields even though they are no longer encoded
// in the GFX11 instruction.
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm);
@@ -713,12 +713,12 @@ DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const {
}
DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
- STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
+ STI.hasFeature(AMDGPU::FeatureGFX10)) {
if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst))
// VOPC - insert clamp
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
- } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
+ } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
if (SDst != -1) {
// VOPC - insert VCC register as sdst
@@ -1517,8 +1517,8 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
using namespace AMDGPU::SDWA;
using namespace AMDGPU::EncValues;
- if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
- STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
+ if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
+ STI.hasFeature(AMDGPU::FeatureGFX10)) {
// XXX: cast to int is needed to avoid stupid warning:
// compare with unsigned is always true
if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
@@ -1547,7 +1547,7 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
return decodeFPImmed(ImmWidth, SVal);
return decodeSpecialReg32(SVal);
- } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
+ } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
return createRegOperand(getVgprClassId(Width), Val);
}
llvm_unreachable("unsupported target");
@@ -1564,11 +1564,11 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
using namespace AMDGPU::SDWA;
- assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
- STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
+ assert((STI.hasFeature(AMDGPU::FeatureGFX9) ||
+ STI.hasFeature(AMDGPU::FeatureGFX10)) &&
"SDWAVopcDst should be present only on GFX9+");
- bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
+ bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64);
if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
@@ -1589,19 +1589,19 @@ MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
}
MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
- return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
+ return STI.hasFeature(AMDGPU::FeatureWavefrontSize64)
? decodeSrcOp(OPW64, Val)
: decodeSrcOp(OPW32, Val);
}
bool AMDGPUDisassembler::isVI() const {
- return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
+ return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
}
bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); }
bool AMDGPUDisassembler::isGFX90A() const {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
+ return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
}
bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); }
@@ -1613,7 +1613,7 @@ bool AMDGPUDisassembler::isGFX10Plus() const {
}
bool AMDGPUDisassembler::isGFX11() const {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX11];
+ return STI.hasFeature(AMDGPU::FeatureGFX11);
}
bool AMDGPUDisassembler::isGFX11Plus() const {
@@ -1622,7 +1622,7 @@ bool AMDGPUDisassembler::isGFX11Plus() const {
bool AMDGPUDisassembler::hasArchitectedFlatScratch() const {
- return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
+ return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
index f6ab28c52986f..44109b9d2919b 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -79,7 +79,7 @@ bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
const MCSubtargetInfo &STI) const {
- if (!STI.getFeatureBits()[AMDGPU::FeatureOffset3fBug])
+ if (!STI.hasFeature(AMDGPU::FeatureOffset3fBug))
return false;
if (AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()) >= 0)
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 182f4a1d4dfcd..a654686e628ba 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -452,7 +452,7 @@ void AMDGPUInstPrinter::printImmediate16(uint32_t Imm,
else if (Imm == 0xC400)
O<< "-4.0";
else if (Imm == 0x3118 &&
- STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) {
+ STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm)) {
O << "0.15915494";
} else {
uint64_t Imm16 = static_cast<uint16_t>(Imm);
@@ -495,7 +495,7 @@ void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
else if (Imm == llvm::bit_cast<uint32_t>(-4.0f))
O << "-4.0";
else if (Imm == 0x3e22f983 &&
- STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+ STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
O << "0.15915494";
else
O << formatHex(static_cast<uint64_t>(Imm));
@@ -529,7 +529,7 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
else if (Imm == llvm::bit_cast<uint64_t>(-4.0))
O << "-4.0";
else if (Imm == 0x3fc45f306dc9c882 &&
- STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+ STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
O << "0.15915494309189532";
else {
assert(isUInt<32>(Imm) || isInt<32>(Imm));
@@ -587,7 +587,7 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
raw_ostream &O) {
if (!FirstOperand)
O << ", ";
- printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
+ printRegOperand(STI.hasFeature(AMDGPU::FeatureWavefrontSize64)
? AMDGPU::VCC
: AMDGPU::VCC_LO,
O, MRI);
@@ -708,7 +708,7 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
case AMDGPU::OPERAND_REG_IMM_V2INT16:
case AMDGPU::OPERAND_REG_IMM_V2FP16:
if (!isUInt<16>(Op.getImm()) &&
- STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) {
+ STI.hasFeature(AMDGPU::FeatureVOP3Literal)) {
printImmediate32(Op.getImm(), STI, O);
break;
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
index c99e47f26a1ba..a988c0412c31e 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
@@ -58,11 +58,11 @@ unsigned AMDGPUMCAsmInfo::getMaxInstLength(const MCSubtargetInfo *STI) const {
return MaxInstLength;
// Maximum for NSA encoded images
- if (STI->getFeatureBits()[AMDGPU::FeatureNSAEncoding])
+ if (STI->hasFeature(AMDGPU::FeatureNSAEncoding))
return 20;
// 64-bit instruction with 32-bit literal.
- if (STI->getFeatureBits()[AMDGPU::FeatureVOP3Literal])
+ if (STI->hasFeature(AMDGPU::FeatureVOP3Literal))
return 12;
return 8;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index 3d926e52c368d..90c81d8ce7a29 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -97,7 +97,7 @@ void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
} else if (IS_VTX(Desc)) {
uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
- if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) {
+ if (!(STI.hasFeature(R600::FeatureCaymanISA))) {
InstWord2 |= 1 << 19; // Mega-Fetch bit
}
@@ -130,7 +130,7 @@ void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
Emit((uint32_t) 0, OS);
} else {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
- if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) &&
+ if ((STI.hasFeature(R600::FeatureR600ALUInst)) &&
((Desc.TSFlags & R600_InstFlag::OP1) ||
Desc.TSFlags & R600_InstFlag::OP2)) {
uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
index 497ac60eaf085..3eb4e5e2c6fcc 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -140,7 +140,7 @@ static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
return 247;
if (Val == 0x3118 && // 1.0 / (2.0 * pi)
- STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+ STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
return 248;
return 255;
@@ -176,7 +176,7 @@ static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
return 247;
if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
- STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+ STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
return 248;
return 255;
@@ -212,7 +212,7 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
return 247;
if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
- STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
+ STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
return 248;
return 255;
@@ -273,7 +273,7 @@ SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
case AMDGPU::OPERAND_REG_IMM_V2INT16:
case AMDGPU::OPERAND_REG_IMM_V2FP16: {
- if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])
+ if (!isUInt<16>(Imm) && STI.hasFeature(AMDGPU::FeatureVOP3Literal))
return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
if (OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)
return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
@@ -367,8 +367,8 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
OS.write(0);
}
- if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) ||
- (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]))
+ if ((bytes > 8 && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) ||
+ (bytes > 4 && !STI.hasFeature(AMDGPU::FeatureVOP3Literal)))
return;
// Do not print literals from SISrc Operands for insts with mandatory literals
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index bb52fd3b1e855..fcc46625014cc 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1919,44 +1919,44 @@ bool isKernelCC(const Function *Func) {
}
bool hasXNACK(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
+ return STI.hasFeature(AMDGPU::FeatureXNACK);
}
bool hasSRAMECC(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
+ return STI.hasFeature(AMDGPU::FeatureSRAMECC);
}
bool hasMIMG_R128(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128A16];
+ return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
}
bool hasA16(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureA16];
+ return STI.hasFeature(AMDGPU::FeatureA16);
}
bool hasG16(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureG16];
+ return STI.hasFeature(AMDGPU::FeatureG16);
}
bool hasPackedD16(const MCSubtargetInfo &STI) {
- return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem] && !isCI(STI) &&
+ return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !isCI(STI) &&
!isSI(STI);
}
bool isSI(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
+ return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
}
bool isCI(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
+ return STI.hasFeature(AMDGPU::FeatureSeaIslands);
}
bool isVI(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
+ return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
}
bool isGFX9(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
+ return STI.hasFeature(AMDGPU::FeatureGFX9);
}
bool isGFX9_GFX10(const MCSubtargetInfo &STI) {
@@ -1976,7 +1976,7 @@ bool isGFX9Plus(const MCSubtargetInfo &STI) {
}
bool isGFX10(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
+ return STI.hasFeature(AMDGPU::FeatureGFX10);
}
bool isGFX10Plus(const MCSubtargetInfo &STI) {
@@ -1984,7 +1984,7 @@ bool isGFX10Plus(const MCSubtargetInfo &STI) {
}
bool isGFX11(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX11];
+ return STI.hasFeature(AMDGPU::FeatureGFX11);
}
bool isGFX11Plus(const MCSubtargetInfo &STI) {
@@ -2004,39 +2004,39 @@ bool isGFX10Before1030(const MCSubtargetInfo &STI) {
}
bool isGCN3Encoding(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
+ return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
}
bool isGFX10_AEncoding(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX10_AEncoding];
+ return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
}
bool isGFX10_BEncoding(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding];
+ return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
}
bool hasGFX10_3Insts(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
+ return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
}
bool isGFX90A(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
+ return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
}
bool isGFX940(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts];
+ return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
}
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
+ return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
}
bool hasMAIInsts(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts];
+ return STI.hasFeature(AMDGPU::FeatureMAIInsts);
}
bool hasVOPD(const MCSubtargetInfo &STI) {
- return STI.getFeatureBits()[AMDGPU::FeatureVOPD];
+ return STI.hasFeature(AMDGPU::FeatureVOPD);
}
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index ad13264999a42..7cd7ee7543a0e 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -466,7 +466,7 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
}
static bool isThumb(const MCSubtargetInfo& STI) {
- return STI.getFeatureBits()[ARM::ModeThumb];
+ return STI.hasFeature(ARM::ModeThumb);
}
void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 1cf6de7585ee5..77557c3f9b5fc 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -5433,7 +5433,7 @@ void ARMBaseInstrInfo::breakPartialRegDependency(
}
bool ARMBaseInstrInfo::hasNOP() const {
- return Subtarget.getFeatureBits()[ARM::HasV6KOps];
+ return Subtarget.hasFeature(ARM::HasV6KOps);
}
bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 75733a9287805..c5003da3e3f9b 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -516,86 +516,86 @@ class ARMAsmParser : public MCTargetAsmParser {
bool isThumb() const {
// FIXME: Can tablegen auto-generate this?
- return getSTI().getFeatureBits()[ARM::ModeThumb];
+ return getSTI().hasFeature(ARM::ModeThumb);
}
bool isThumbOne() const {
- return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
+ return isThumb() && !getSTI().hasFeature(ARM::FeatureThumb2);
}
bool isThumbTwo() const {
- return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
+ return isThumb() && getSTI().hasFeature(ARM::FeatureThumb2);
}
bool hasThumb() const {
- return getSTI().getFeatureBits()[ARM::HasV4TOps];
+ return getSTI().hasFeature(ARM::HasV4TOps);
}
bool hasThumb2() const {
- return getSTI().getFeatureBits()[ARM::FeatureThumb2];
+ return getSTI().hasFeature(ARM::FeatureThumb2);
}
bool hasV6Ops() const {
- return getSTI().getFeatureBits()[ARM::HasV6Ops];
+ return getSTI().hasFeature(ARM::HasV6Ops);
}
bool hasV6T2Ops() const {
- return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
+ return getSTI().hasFeature(ARM::HasV6T2Ops);
}
bool hasV6MOps() const {
- return getSTI().getFeatureBits()[ARM::HasV6MOps];
+ return getSTI().hasFeature(ARM::HasV6MOps);
}
bool hasV7Ops() const {
- return getSTI().getFeatureBits()[ARM::HasV7Ops];
+ return getSTI().hasFeature(ARM::HasV7Ops);
}
bool hasV8Ops() const {
- return getSTI().getFeatureBits()[ARM::HasV8Ops];
+ return getSTI().hasFeature(ARM::HasV8Ops);
}
bool hasV8MBaseline() const {
- return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
+ return getSTI().hasFeature(ARM::HasV8MBaselineOps);
}
bool hasV8MMainline() const {
- return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
+ return getSTI().hasFeature(ARM::HasV8MMainlineOps);
}
bool hasV8_1MMainline() const {
- return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps];
+ return getSTI().hasFeature(ARM::HasV8_1MMainlineOps);
}
bool hasMVE() const {
- return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps];
+ return getSTI().hasFeature(ARM::HasMVEIntegerOps);
}
bool hasMVEFloat() const {
- return getSTI().getFeatureBits()[ARM::HasMVEFloatOps];
+ return getSTI().hasFeature(ARM::HasMVEFloatOps);
}
bool hasCDE() const {
- return getSTI().getFeatureBits()[ARM::HasCDEOps];
+ return getSTI().hasFeature(ARM::HasCDEOps);
}
bool has8MSecExt() const {
- return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
+ return getSTI().hasFeature(ARM::Feature8MSecExt);
}
bool hasARM() const {
- return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
+ return !getSTI().hasFeature(ARM::FeatureNoARM);
}
bool hasDSP() const {
- return getSTI().getFeatureBits()[ARM::FeatureDSP];
+ return getSTI().hasFeature(ARM::FeatureDSP);
}
bool hasD32() const {
- return getSTI().getFeatureBits()[ARM::FeatureD32];
+ return getSTI().hasFeature(ARM::FeatureD32);
}
bool hasV8_1aOps() const {
- return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
+ return getSTI().hasFeature(ARM::HasV8_1aOps);
}
bool hasRAS() const {
- return getSTI().getFeatureBits()[ARM::FeatureRAS];
+ return getSTI().hasFeature(ARM::FeatureRAS);
}
void SwitchMode() {
@@ -607,7 +607,7 @@ class ARMAsmParser : public MCTargetAsmParser {
void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
bool isMClass() const {
- return getSTI().getFeatureBits()[ARM::FeatureMClass];
+ return getSTI().hasFeature(ARM::FeatureMClass);
}
/// @name Auto-generated Match Functions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 38c291cf82101..e4928013f969c 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -135,7 +135,7 @@ class ARMDisassembler : public MCDisassembler {
ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
const MCInstrInfo *MCII)
: MCDisassembler(STI, Ctx), MCII(MCII) {
- InstructionEndianness = STI.getFeatureBits()[ARM::ModeBigEndianInstructions]
+ InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions)
? llvm::support::big
: llvm::support::little;
}
@@ -746,7 +746,7 @@ uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
// In Arm state, instructions are always 4 bytes wide, so there's no
// point in skipping any smaller number of bytes if an instruction
// can't be decoded.
- if (!STI.getFeatureBits()[ARM::ModeThumb])
+ if (!STI.hasFeature(ARM::ModeThumb))
return 4;
// In a Thumb instruction stream, a halfword is a standalone 2-byte
@@ -773,7 +773,7 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes,
uint64_t Address,
raw_ostream &CS) const {
- if (STI.getFeatureBits()[ARM::ModeThumb])
+ if (STI.hasFeature(ARM::ModeThumb))
return getThumbInstruction(MI, Size, Bytes, Address, CS);
return getARMInstruction(MI, Size, Bytes, Address, CS);
}
@@ -784,7 +784,7 @@ DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size,
raw_ostream &CS) const {
CommentStream = &CS;
- assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
+ assert(!STI.hasFeature(ARM::ModeThumb) &&
"Asked to disassemble an ARM instruction but Subtarget is in Thumb "
"mode!");
@@ -1070,7 +1070,7 @@ DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size,
raw_ostream &CS) const {
CommentStream = &CS;
- assert(STI.getFeatureBits()[ARM::ModeThumb] &&
+ assert(STI.hasFeature(ARM::ModeThumb) &&
"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
// We want to read exactly 2 bytes of data.
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 8b2263560d200..d694385098583 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -208,8 +208,8 @@ void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op,
const MCSubtargetInfo &STI) const {
- bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
- bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
+ bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2);
+ bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps);
switch (Op) {
default:
@@ -604,9 +604,9 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
}
case ARM::fixup_arm_thumb_bl: {
if (!isInt<25>(Value - 4) ||
- (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
- !STI->getFeatureBits()[ARM::HasV8MBaselineOps] &&
- !STI->getFeatureBits()[ARM::HasV6MOps] &&
+ (!STI->hasFeature(ARM::FeatureThumb2) &&
+ !STI->hasFeature(ARM::HasV8MBaselineOps) &&
+ !STI->hasFeature(ARM::HasV6MOps) &&
!isInt<23>(Value - 4))) {
Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
return 0;
@@ -679,7 +679,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
// On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
// could have an error on our hands.
assert(STI != nullptr);
- if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
+ if (!STI->hasFeature(ARM::FeatureThumb2) && IsResolved) {
const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
if (FixupDiagnostic) {
Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
@@ -704,8 +704,8 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
case ARM::fixup_arm_thumb_br:
// Offset by 4 and don't encode the lower bit, which is always 0.
assert(STI != nullptr);
- if (!STI->getFeatureBits()[ARM::FeatureThumb2] &&
- !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
+ if (!STI->hasFeature(ARM::FeatureThumb2) &&
+ !STI->hasFeature(ARM::HasV8MBaselineOps)) {
const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
if (FixupDiagnostic) {
Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
@@ -716,7 +716,7 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
case ARM::fixup_arm_thumb_bcc:
// Offset by 4 and don't encode the lower bit, which is always 0.
assert(STI != nullptr);
- if (!STI->getFeatureBits()[ARM::FeatureThumb2]) {
+ if (!STI->hasFeature(ARM::FeatureThumb2)) {
const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
if (FixupDiagnostic) {
Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
index a952823d1aad9..64c78d3528955 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
@@ -28,7 +28,7 @@ class ARMAsmBackend : public MCAsmBackend {
}
bool hasNOP(const MCSubtargetInfo *STI) const {
- return STI->getFeatureBits()[ARM::HasV6T2Ops];
+ return STI->hasFeature(ARM::HasV6T2Ops);
}
std::optional<MCFixupKind> getFixupKind(StringRef Name) const override;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index 737c373b14335..d501e373fa45c 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -750,7 +750,7 @@ void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned val = MI->getOperand(OpNum).getImm();
- O << ARM_MB::MemBOptToString(val, STI.getFeatureBits()[ARM::HasV8Ops]);
+ O << ARM_MB::MemBOptToString(val, STI.hasFeature(ARM::HasV8Ops));
}
void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 8c8384648dd26..6843b130c90e7 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -61,11 +61,11 @@ class ARMMCCodeEmitter : public MCCodeEmitter {
~ARMMCCodeEmitter() override = default;
bool isThumb(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits()[ARM::ModeThumb];
+ return STI.hasFeature(ARM::ModeThumb);
}
bool isThumb2(const MCSubtargetInfo &STI) const {
- return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
+ return isThumb(STI) && STI.hasFeature(ARM::FeatureThumb2);
}
bool isTargetMachO(const MCSubtargetInfo &STI) const {
@@ -562,7 +562,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
// the encodings all refer to Q-registers by their literal
// register number.
- if (STI.getFeatureBits()[ARM::HasMVEIntegerOps])
+ if (STI.hasFeature(ARM::HasMVEIntegerOps))
return RegNo;
switch (Reg) {
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index ffe604dc51855..e8dad61aabbcd 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -38,7 +38,7 @@ using namespace llvm;
static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
std::string &Info) {
- if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
+ if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) &&
(MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) &&
// Checks for the deprecated CP15ISB encoding:
@@ -65,7 +65,7 @@ static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
return true;
}
}
- if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
+ if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
@@ -77,7 +77,7 @@ static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
std::string &Info) {
- if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
+ if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
(MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
@@ -89,7 +89,7 @@ static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
std::string &Info) {
- assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
+ assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
"cannot predicate thumb instructions");
assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
@@ -105,7 +105,7 @@ static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
std::string &Info) {
- assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
+ assert(!STI.hasFeature(llvm::ARM::ModeThumb) &&
"cannot predicate thumb instructions");
assert(MI.getNumOperands() >= 4 && "expected >= 4 arguments");
@@ -598,7 +598,7 @@ std::optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
// VLDR* instructions share the same opcode (and thus the same form) for Arm
// and Thumb. Use a bit longer route through STI in that case.
case ARMII::VFPLdStFrm:
- Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8;
+ Addr += STI->hasFeature(ARM::ModeThumb) ? 4 : 8;
break;
}
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index df047ed8ecae0..07121ec29fff6 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -489,7 +489,7 @@ DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
return MCDisassembler::Fail;
// Try to decode AVRTiny instructions.
- if (STI.getFeatureBits()[AVR::FeatureTinyEncoding]) {
+ if (STI.hasFeature(AVR::FeatureTinyEncoding)) {
Result = decodeInstruction(DecoderTableAVRTiny16, Instr, Insn, Address,
this, STI);
if (Result != MCDisassembler::Fail)
diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
index aa408f8b65f75..f5b511e471cd5 100644
--- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
+++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
@@ -179,7 +179,7 @@ DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
if ((InstClass == BPF_LDX || InstClass == BPF_STX) &&
getInstSize(Insn) != BPF_DW &&
(InstMode == BPF_MEM || InstMode == BPF_ATOMIC) &&
- STI.getFeatureBits()[BPF::ALU32])
+ STI.hasFeature(BPF::ALU32))
Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address,
this, STI);
else
diff --git a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
index cad1625ca2159..5198399a4ebf7 100644
--- a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
+++ b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
@@ -835,7 +835,7 @@ bool CSKYAsmParser::processLRW(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out) {
if (isUInt<8>(Inst.getOperand(1).getImm()) &&
Inst.getOperand(0).getReg() <= CSKY::R7) {
Opcode = CSKY::MOVI16;
- } else if (getSTI().getFeatureBits()[CSKY::HasE2] &&
+ } else if (getSTI().hasFeature(CSKY::HasE2) &&
isUInt<16>(Inst.getOperand(1).getImm())) {
Opcode = CSKY::MOVI32;
} else {
diff --git a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
index ce0f63b99d688..d78d9acc2aa23 100644
--- a/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
+++ b/llvm/lib/Target/CSKY/Disassembler/CSKYDisassembler.cpp
@@ -496,9 +496,9 @@ static bool decodeFPUV3Instruction(MCInst &MI, uint32_t insn, uint64_t Address,
const MCDisassembler *DisAsm,
const MCSubtargetInfo &STI) {
LLVM_DEBUG(dbgs() << "Trying CSKY 32-bit fpuv3 table :\n");
- if (!STI.getFeatureBits()[CSKY::FeatureFPUV3_HF] &&
- !STI.getFeatureBits()[CSKY::FeatureFPUV3_SF] &&
- !STI.getFeatureBits()[CSKY::FeatureFPUV3_DF])
+ if (!STI.hasFeature(CSKY::FeatureFPUV3_HF) &&
+ !STI.hasFeature(CSKY::FeatureFPUV3_SF) &&
+ !STI.hasFeature(CSKY::FeatureFPUV3_DF))
return false;
DecodeStatus Result =
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
index 4171a97e9000d..d53d2e9e00e92 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
@@ -248,7 +248,7 @@ bool CSKYAsmBackend::mayNeedRelaxation(const MCInst &Inst,
case CSKY::JBT32:
case CSKY::JBF32:
case CSKY::JBSR32:
- if (!STI.getFeatureBits()[CSKY::Has2E3])
+ if (!STI.hasFeature(CSKY::Has2E3))
return false;
return true;
case CSKY::JBR16:
@@ -330,7 +330,7 @@ void CSKYAsmBackend::relaxInstruction(MCInst &Inst,
case CSKY::JBF16:
// ck801
unsigned opcode;
- if (STI.getFeatureBits()[CSKY::HasE2])
+ if (STI.hasFeature(CSKY::HasE2))
opcode = Inst.getOpcode() == CSKY::JBT16 ? CSKY::JBT32 : CSKY::JBF32;
else
opcode = Inst.getOpcode() == CSKY::JBT16 ? CSKY::JBT_E : CSKY::JBF_E;
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
index 3e4fdb5e67c34..9af7958112fce 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
@@ -113,7 +113,7 @@ void CSKYInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
if (Reg == CSKY::C)
O << "";
- else if (STI.getFeatureBits()[CSKY::FeatureJAVA]) {
+ else if (STI.hasFeature(CSKY::FeatureJAVA)) {
if (Reg == CSKY::R23)
O << (useABIName ? "fp" : "r23");
else if (Reg == CSKY::R24)
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
index 540f901fd479d..ea41d53ef30fd 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
@@ -82,7 +82,7 @@ void CSKYMCCodeEmitter::expandJBTF(const MCInst &MI, raw_ostream &OS,
Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
writeData(Binary, 2, OS);
- if (!STI.getFeatureBits()[CSKY::Has2E3])
+ if (!STI.hasFeature(CSKY::Has2E3))
TmpInst = MCInstBuilder(CSKY::BR32)
.addOperand(MI.getOperand(1))
.addOperand(MI.getOperand(2));
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
index 9a2cf94edfe66..ce93715d6c42d 100644
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -516,7 +516,7 @@ bool HexagonAsmParser::matchBundleOptions() {
} else if (Option.compare_insensitive("endloop1") == 0) {
HexagonMCInstrInfo::setOuterLoop(MCB);
} else if (Option.compare_insensitive("mem_noshuf") == 0) {
- if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
+ if (getSTI().hasFeature(Hexagon::FeatureMemNoShuf))
HexagonMCInstrInfo::setMemReorderDisabled(MCB);
else
return getParser().Error(IDLoc, MemNoShuffMsg);
@@ -813,7 +813,7 @@ bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
// validate register against architecture
bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
- if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
+ if (!getSTI().hasFeature(Hexagon::ArchV62))
return false;
return true;
}
@@ -1329,7 +1329,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
break;
case Hexagon::J2_trap1:
- if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
+ if (!getSTI().hasFeature(Hexagon::ArchV65)) {
MCOperand &Rx = Inst.getOperand(0);
MCOperand &Ry = Inst.getOperand(1);
if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) {
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index de6ca0aa9cbb4..c7e22d7d308b0 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -428,7 +428,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
STI);
if (Result != MCDisassembler::Success &&
- STI.getFeatureBits()[Hexagon::ExtensionHVX])
+ STI.hasFeature(Hexagon::ExtensionHVX))
Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
Address, this, STI);
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index a636f7c4264e9..a2500c188b298 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -3844,7 +3844,7 @@ int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
// All Hexagon architectures have prediction bits on dot-new branches,
// but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
// to pick the right opcode when converting back to dot-old.
- if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) {
+ if (!Subtarget.hasFeature(Hexagon::ArchV60)) {
switch (NewOp) {
case Hexagon::J2_jumptpt:
NewOp = Hexagon::J2_jumpt;
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
index 080f71ea28e11..ec84e0ddc259d 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
@@ -103,7 +103,7 @@ void HexagonMCChecker::init(MCInst const &MCI) {
const bool IgnoreTmpDst = (HexagonMCInstrInfo::hasTmpDst(MCII, MCI) ||
HexagonMCInstrInfo::hasHvxTmp(MCII, MCI)) &&
- STI.getFeatureBits()[Hexagon::ArchV69];
+ STI.hasFeature(Hexagon::ArchV69);
// Get implicit register definitions.
for (MCPhysReg R : MCID.implicit_defs()) {
@@ -709,7 +709,7 @@ bool HexagonMCChecker::checkShuffle() {
}
bool HexagonMCChecker::checkValidTmpDst() {
- if (!STI.getFeatureBits()[Hexagon::ArchV69]) {
+ if (!STI.hasFeature(Hexagon::ArchV69)) {
return true;
}
auto HasTmp = [&](MCInst const &I) {
@@ -799,7 +799,7 @@ void HexagonMCChecker::reportWarning(Twine const &Msg) {
}
bool HexagonMCChecker::checkLegalVecRegPair() {
- const bool IsPermitted = STI.getFeatureBits()[Hexagon::ArchV67];
+ const bool IsPermitted = STI.hasFeature(Hexagon::ArchV67);
const bool HasReversePairs = ReversePairs.size() != 0;
if (!IsPermitted && HasReversePairs) {
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index ef1ccea6add7a..0fd002ac56909 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -138,7 +138,7 @@ bool canonicalizePacketImpl(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
HexagonMCShuffle(Context, false, MCII, STI, MCB);
const SmallVector<DuplexCandidate, 8> possibleDuplexes =
- (STI.getFeatureBits()[Hexagon::FeatureDuplex])
+ (STI.hasFeature(Hexagon::FeatureDuplex))
? HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB)
: SmallVector<DuplexCandidate, 8>();
@@ -907,7 +907,7 @@ bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
}
unsigned HexagonMCInstrInfo::packetSizeSlots(MCSubtargetInfo const &STI) {
- const bool IsTiny = STI.getFeatureBits()[Hexagon::ProcTinyCore];
+ const bool IsTiny = STI.hasFeature(Hexagon::ProcTinyCore);
return IsTiny ? (HEXAGON_PACKET_SIZE - 1) : HEXAGON_PACKET_SIZE;
}
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 6c9a3eb4b3463..cf6fa78a20051 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -364,12 +364,12 @@ static MCTargetStreamer *createHexagonNullTargetStreamer(MCStreamer &S) {
}
static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) {
- if (STI->getFeatureBits()[F])
+ if (STI->hasFeature(F))
STI->ToggleFeature(F);
}
static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) {
- return STI->getFeatureBits()[F];
+ return STI->hasFeature(F);
}
namespace {
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 909058e2925fe..73cbd63376fa4 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -2209,8 +2209,8 @@ SDValue LoongArchTargetLowering::LowerFormalArguments(
case CallingConv::Fast:
break;
case CallingConv::GHC:
- if (!MF.getSubtarget().getFeatureBits()[LoongArch::FeatureBasicF] ||
- !MF.getSubtarget().getFeatureBits()[LoongArch::FeatureBasicD])
+ if (!MF.getSubtarget().hasFeature(LoongArch::FeatureBasicF) ||
+ !MF.getSubtarget().hasFeature(LoongArch::FeatureBasicD))
report_fatal_error(
"GHC calling convention requires the F and D extensions");
}
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index c0f5116a6502e..fa6ddf5007b06 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -482,7 +482,7 @@ class MipsAsmParser : public MCTargetAsmParser {
}
void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
- if (!(getSTI().getFeatureBits()[Feature])) {
+ if (!(getSTI().hasFeature(Feature))) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
@@ -491,7 +491,7 @@ class MipsAsmParser : public MCTargetAsmParser {
}
void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
- if (getSTI().getFeatureBits()[Feature]) {
+ if (getSTI().hasFeature(Feature)) {
MCSubtargetInfo &STI = copySTI();
setAvailableFeatures(
ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
@@ -576,11 +576,11 @@ class MipsAsmParser : public MCTargetAsmParser {
bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
bool isGP64bit() const {
- return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
+ return getSTI().hasFeature(Mips::FeatureGP64Bit);
}
bool isFP64bit() const {
- return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
+ return getSTI().hasFeature(Mips::FeatureFP64Bit);
}
bool isJalrRelocAvailable(const MCExpr *JalExpr) {
@@ -601,99 +601,99 @@ class MipsAsmParser : public MCTargetAsmParser {
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
bool isABI_FPXX() const {
- return getSTI().getFeatureBits()[Mips::FeatureFPXX];
+ return getSTI().hasFeature(Mips::FeatureFPXX);
}
bool useOddSPReg() const {
- return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
+ return !(getSTI().hasFeature(Mips::FeatureNoOddSPReg));
}
bool inMicroMipsMode() const {
- return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
+ return getSTI().hasFeature(Mips::FeatureMicroMips);
}
bool hasMips1() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips1];
+ return getSTI().hasFeature(Mips::FeatureMips1);
}
bool hasMips2() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips2];
+ return getSTI().hasFeature(Mips::FeatureMips2);
}
bool hasMips3() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips3];
+ return getSTI().hasFeature(Mips::FeatureMips3);
}
bool hasMips4() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips4];
+ return getSTI().hasFeature(Mips::FeatureMips4);
}
bool hasMips5() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips5];
+ return getSTI().hasFeature(Mips::FeatureMips5);
}
bool hasMips32() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips32];
+ return getSTI().hasFeature(Mips::FeatureMips32);
}
bool hasMips64() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips64];
+ return getSTI().hasFeature(Mips::FeatureMips64);
}
bool hasMips32r2() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
+ return getSTI().hasFeature(Mips::FeatureMips32r2);
}
bool hasMips64r2() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
+ return getSTI().hasFeature(Mips::FeatureMips64r2);
}
bool hasMips32r3() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
+ return (getSTI().hasFeature(Mips::FeatureMips32r3));
}
bool hasMips64r3() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
+ return (getSTI().hasFeature(Mips::FeatureMips64r3));
}
bool hasMips32r5() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
+ return (getSTI().hasFeature(Mips::FeatureMips32r5));
}
bool hasMips64r5() const {
- return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
+ return (getSTI().hasFeature(Mips::FeatureMips64r5));
}
bool hasMips32r6() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
+ return getSTI().hasFeature(Mips::FeatureMips32r6);
}
bool hasMips64r6() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
+ return getSTI().hasFeature(Mips::FeatureMips64r6);
}
bool hasDSP() const {
- return getSTI().getFeatureBits()[Mips::FeatureDSP];
+ return getSTI().hasFeature(Mips::FeatureDSP);
}
bool hasDSPR2() const {
- return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
+ return getSTI().hasFeature(Mips::FeatureDSPR2);
}
bool hasDSPR3() const {
- return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
+ return getSTI().hasFeature(Mips::FeatureDSPR3);
}
bool hasMSA() const {
- return getSTI().getFeatureBits()[Mips::FeatureMSA];
+ return getSTI().hasFeature(Mips::FeatureMSA);
}
bool hasCnMips() const {
- return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
+ return (getSTI().hasFeature(Mips::FeatureCnMips));
}
bool hasCnMipsP() const {
- return (getSTI().getFeatureBits()[Mips::FeatureCnMipsP]);
+ return (getSTI().hasFeature(Mips::FeatureCnMipsP));
}
bool inPicMode() {
@@ -701,30 +701,30 @@ class MipsAsmParser : public MCTargetAsmParser {
}
bool inMips16Mode() const {
- return getSTI().getFeatureBits()[Mips::FeatureMips16];
+ return getSTI().hasFeature(Mips::FeatureMips16);
}
bool useTraps() const {
- return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
+ return getSTI().hasFeature(Mips::FeatureUseTCCInDIV);
}
bool useSoftFloat() const {
- return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
+ return getSTI().hasFeature(Mips::FeatureSoftFloat);
}
bool hasMT() const {
- return getSTI().getFeatureBits()[Mips::FeatureMT];
+ return getSTI().hasFeature(Mips::FeatureMT);
}
bool hasCRC() const {
- return getSTI().getFeatureBits()[Mips::FeatureCRC];
+ return getSTI().hasFeature(Mips::FeatureCRC);
}
bool hasVirt() const {
- return getSTI().getFeatureBits()[Mips::FeatureVirt];
+ return getSTI().hasFeature(Mips::FeatureVirt);
}
bool hasGINV() const {
- return getSTI().getFeatureBits()[Mips::FeatureGINV];
+ return getSTI().hasFeature(Mips::FeatureGINV);
}
/// Warn if RegIndex is the same as the current AT.
@@ -2924,7 +2924,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
(Res.getSymA()->getSymbol().isELF() &&
cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
ELF::STB_LOCAL);
- bool UseXGOT = STI->getFeatureBits()[Mips::FeatureXGOT] && !IsLocalSym;
+ bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;
// The case where the result register is $25 is somewhat special. If the
// symbol in the final relocation is external and not modified with a
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index fb92590350c75..cda288a25aed5 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -44,26 +44,26 @@ class MipsDisassembler : public MCDisassembler {
public:
MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
: MCDisassembler(STI, Ctx),
- IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
+ IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)),
IsBigEndian(IsBigEndian) {}
- bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
- bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
- bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
+ bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); }
+ bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); }
+ bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); }
bool hasMips32r6() const {
- return STI.getFeatureBits()[Mips::FeatureMips32r6];
+ return STI.hasFeature(Mips::FeatureMips32r6);
}
- bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
+ bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); }
- bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
+ bool isGP64() const { return STI.hasFeature(Mips::FeatureGP64Bit); }
- bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
+ bool isPTR64() const { return STI.hasFeature(Mips::FeaturePTR64Bit); }
- bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
+ bool hasCnMips() const { return STI.hasFeature(Mips::FeatureCnMips); }
- bool hasCnMipsP() const { return STI.getFeatureBits()[Mips::FeatureCnMipsP]; }
+ bool hasCnMipsP() const { return STI.hasFeature(Mips::FeatureCnMipsP); }
bool hasCOP3() const {
// Only present in MIPS-I and MIPS-II
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 781f1097176d4..1c7440dfbe91c 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -116,11 +116,11 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
}
bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits()[Mips::FeatureMicroMips];
+ return STI.hasFeature(Mips::FeatureMicroMips);
}
bool MipsMCCodeEmitter::isMips32r6(const MCSubtargetInfo &STI) const {
- return STI.getFeatureBits()[Mips::FeatureMips32r6];
+ return STI.hasFeature(Mips::FeatureMips32r6);
}
void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
index 9893c6055f81c..d0aa14a1b724a 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -37,11 +37,11 @@ static cl::opt<bool> RoundSectionSizes(
} // end anonymous namespace
static bool isMicroMips(const MCSubtargetInfo *STI) {
- return STI->getFeatureBits()[Mips::FeatureMicroMips];
+ return STI->hasFeature(Mips::FeatureMicroMips);
}
static bool isMips32r6(const MCSubtargetInfo *STI) {
- return STI->getFeatureBits()[Mips::FeatureMips32r6];
+ return STI->hasFeature(Mips::FeatureMips32r6);
}
MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 726aa28915e0c..42cf674632f46 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1200,7 +1200,7 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
break;
}
case PPC::MFTB: {
- if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
+ if (getSTI().hasFeature(PPC::FeatureMFTB)) {
assert(Inst.getNumOperands() == 2 && "Expecting two operands");
Inst.setOpcode(PPC::MFSPR);
}
@@ -1642,7 +1642,7 @@ bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
// where th can be omitted when it is 0. dcbtst is the same. We take the
// server form to be the default, so swap the operands if we're parsing for
// an embedded core (they'll be swapped again upon printing).
- if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
+ if (getSTI().hasFeature(PPC::FeatureBookE) &&
Operands.size() == 4 &&
(Name == "dcbt" || Name == "dcbtst")) {
std::swap(Operands[1], Operands[3]);
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index f8ff863f29c9c..9faad9b742097 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -363,7 +363,7 @@ DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
// TODO: In this function we call decodeInstruction several times with
//
diff erent decoder tables. It may be possible to only call once by
// looking at the top 6 bits of the instruction.
- if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
+ if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {
uint32_t Prefix = ReadFunc(Bytes.data());
uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
@@ -385,7 +385,7 @@ DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
// Read the instruction in the proper endianness.
uint64_t Inst = ReadFunc(Bytes.data());
- if (STI.getFeatureBits()[PPC::FeatureSPE]) {
+ if (STI.hasFeature(PPC::FeatureSPE)) {
DecodeStatus result =
decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
if (result != MCDisassembler::Fail)
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
index 064d3d6916db8..dbdfb6e906bbe 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -161,7 +161,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// On AIX, only emit the extended mnemonics for dcbt and dcbtst if
// the "modern assembler" is available.
if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
- (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
+ (!TT.isOSAIX() || STI.hasFeature(PPC::FeatureModernAIXAs))) {
unsigned char TH = MI->getOperand(0).getImm();
O << "\tdcbt";
if (MI->getOpcode() == PPC::DCBTST)
@@ -170,7 +170,7 @@ void PPCInstPrinter::printInst(const MCInst *MI, uint64_t Address,
O << "t";
O << " ";
- bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
+ bool IsBookE = STI.hasFeature(PPC::FeatureBookE);
if (IsBookE && TH != 0 && TH != 16)
O << (unsigned int) TH << ", ";
diff --git a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index 496c08f76a16e..b7581c1979d82 100644
--- a/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -302,7 +302,7 @@ DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
// Calling the auto-generated decoder function.
- if (STI.getFeatureBits()[Sparc::FeatureV9])
+ if (STI.hasFeature(Sparc::FeatureV9))
{
Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
}
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
index fb22ddd91ba0e..c78260d38c4ee 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp
@@ -35,7 +35,7 @@ namespace Sparc {
#include "SparcGenAsmWriter.inc"
bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
- return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0;
+ return (STI.hasFeature(Sparc::FeatureV9)) != 0;
}
void SparcInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index 3e63f17c6518d..2bfde5130c820 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -760,7 +760,7 @@ void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
void SystemZAsmPrinter::emitAttributes(Module &M) {
if (M.getModuleFlag("s390x-visible-vector-ABI")) {
bool HasVectorFeature =
- TM.getMCSubtargetInfo()->getFeatureBits()[SystemZ::FeatureVector];
+ TM.getMCSubtargetInfo()->hasFeature(SystemZ::FeatureVector);
OutStreamer->emitGNUAttribute(8, HasVectorFeature ? 2 : 1);
}
}
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index b45be0d842ddc..56a82f9144a98 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1210,15 +1210,15 @@ class X86AsmParser : public MCTargetAsmParser {
bool is64BitMode() const {
// FIXME: Can tablegen auto-generate this?
- return getSTI().getFeatureBits()[X86::Is64Bit];
+ return getSTI().hasFeature(X86::Is64Bit);
}
bool is32BitMode() const {
// FIXME: Can tablegen auto-generate this?
- return getSTI().getFeatureBits()[X86::Is32Bit];
+ return getSTI().hasFeature(X86::Is32Bit);
}
bool is16BitMode() const {
// FIXME: Can tablegen auto-generate this?
- return getSTI().getFeatureBits()[X86::Is16Bit];
+ return getSTI().hasFeature(X86::Is16Bit);
}
void SwitchMode(unsigned mode) {
MCSubtargetInfo &STI = copySTI();
@@ -4045,13 +4045,13 @@ void X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
MCStreamer &Out) {
if (LVIInlineAsmHardening &&
- getSTI().getFeatureBits()[X86::FeatureLVIControlFlowIntegrity])
+ getSTI().hasFeature(X86::FeatureLVIControlFlowIntegrity))
applyLVICFIMitigation(Inst, Out);
Out.emitInstruction(Inst, getSTI());
if (LVIInlineAsmHardening &&
- getSTI().getFeatureBits()[X86::FeatureLVILoadHardening])
+ getSTI().hasFeature(X86::FeatureLVILoadHardening))
applyLVILoadHardeningMitigation(Inst, Out);
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
index 5a1c4ec81e1bf..21a3fe19819c5 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp
@@ -55,7 +55,7 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// InstrInfo.td as soon as Requires clause is supported properly
// for InstAlias.
if (MI->getOpcode() == X86::CALLpcrel32 &&
- (STI.getFeatureBits()[X86::Is64Bit])) {
+ (STI.hasFeature(X86::Is64Bit))) {
OS << "\tcallq\t";
printPCRelImm(MI, Address, 0, OS);
}
@@ -65,7 +65,7 @@ void X86ATTInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// 0x66 to be interpreted as "data16" by the asm printer.
// Thus we add an adjustment here in order to print the "right" instruction.
else if (MI->getOpcode() == X86::DATA16_PREFIX &&
- STI.getFeatureBits()[X86::Is16Bit]) {
+ STI.hasFeature(X86::Is16Bit)) {
OS << "\tdata32";
}
// Try to print any aliases first.
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
index 67f93ae7bfbee..b50a40edc209f 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -754,7 +754,7 @@ bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
void X86AsmBackend::relaxInstruction(MCInst &Inst,
const MCSubtargetInfo &STI) const {
// The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
- bool Is16BitMode = STI.getFeatureBits()[X86::Is16Bit];
+ bool Is16BitMode = STI.hasFeature(X86::Is16Bit);
unsigned RelaxedOp = getRelaxedOpcode(Inst, Is16BitMode);
if (RelaxedOp == Inst.getOpcode()) {
@@ -773,7 +773,7 @@ void X86AsmBackend::relaxInstruction(MCInst &Inst,
static bool isFullyRelaxed(const MCRelaxableFragment &RF) {
auto &Inst = RF.getInst();
auto &STI = *RF.getSubtargetInfo();
- bool Is16BitMode = STI.getFeatureBits()[X86::Is16Bit];
+ bool Is16BitMode = STI.hasFeature(X86::Is16Bit);
return getRelaxedOpcode(Inst, Is16BitMode) == Inst.getOpcode();
}
@@ -1001,11 +1001,11 @@ unsigned X86AsmBackend::getMaximumNopSize(const MCSubtargetInfo &STI) const {
return 4;
if (!STI.hasFeature(X86::FeatureNOPL) && !STI.hasFeature(X86::Is64Bit))
return 1;
- if (STI.getFeatureBits()[X86::TuningFast7ByteNOP])
+ if (STI.hasFeature(X86::TuningFast7ByteNOP))
return 7;
- if (STI.getFeatureBits()[X86::TuningFast15ByteNOP])
+ if (STI.hasFeature(X86::TuningFast15ByteNOP))
return 15;
- if (STI.getFeatureBits()[X86::TuningFast11ByteNOP])
+ if (STI.hasFeature(X86::TuningFast11ByteNOP))
return 11;
// FIXME: handle 32-bit mode
// 15-bytes is the longest single NOP instruction, but 10-bytes is
@@ -1054,7 +1054,7 @@ bool X86AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
};
const char(*Nops)[11] =
- STI->getFeatureBits()[X86::Is16Bit] ? Nops16Bit : Nops32Bit;
+ STI->hasFeature(X86::Is16Bit) ? Nops16Bit : Nops32Bit;
uint64_t MaxNopLength = (uint64_t)getMaximumNopSize(*STI);
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
index a8ef195cba78b..8cfe0e13beabf 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -44,7 +44,7 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
// In 16-bit mode, print data16 as data32.
if (MI->getOpcode() == X86::DATA16_PREFIX &&
- STI.getFeatureBits()[X86::Is16Bit]) {
+ STI.hasFeature(X86::Is16Bit)) {
OS << "\tdata32";
} else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
printInstruction(MI, Address, OS);
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index 3e68a955daa4a..2d36b94dd40c7 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -39,7 +39,7 @@ class XtensaDisassembler : public MCDisassembler {
: MCDisassembler(STI, Ctx), IsLittleEndian(isLE) {}
bool hasDensity() const {
- return STI.getFeatureBits()[Xtensa::FeatureDensity];
+ return STI.hasFeature(Xtensa::FeatureDensity);
}
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
More information about the llvm-commits
mailing list