[PATCH] D144278: [RISCV] xtheadmac: fix commutativity issue for the in/out register

[Philipp Tomsich via Phabricator via llvm-commits]

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The instructions in the XTHeadMac extension (multiply accumulate
instructions) were marked as commutative but because the destination
register was also an input (accumulate) register and was connected to
the destination register with a register allocator constraint, all
three operands (instead of two) were incorrectly considered
commutative. To fix that an appropriate fixCommutedOpIndices call was
added for these instructions in findCommutedOpIndices

New test functions have been added to test the correct behaviour in
xtheadmac.ll.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144278

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/bitextract-mac.ll
  llvm/test/CodeGen/RISCV/xtheadmac.ll

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