[llvm] 22b564c - [RISCV] Add preferred function and loop alignment RISCVSubtarget. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-02-17T08:43:40-08:00
New Revision: 22b564c64b736f5a422b3967720c871c8f9eee9b

URL: https://github.com/llvm/llvm-project/commit/22b564c64b736f5a422b3967720c871c8f9eee9b
DIFF: https://github.com/llvm/llvm-project/commit/22b564c64b736f5a422b3967720c871c8f9eee9b.diff

LOG: [RISCV] Add preferred function and loop alignment RISCVSubtarget. NFC

These seem like properties we will want to adjust based on -mtune.
Move them to subtarget like is done on ARM and AArch64. Don't add
any overrides yet.

Note there's a slight change here. We are now passing Align(1) for
preferred function alignment where we previously passed the minimum
alignment. As far as I could tell, it will be maxed with min when
it used so this should be ok.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D144048

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/lib/Target/RISCV/RISCVSubtarget.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bfeea59a862c..087dd3b4ddd7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1014,7 +1014,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   // Function alignments.
   const Align FunctionAlignment(Subtarget.hasStdExtCOrZca() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
-  setPrefFunctionAlignment(FunctionAlignment);
+  // Set preferred alignments.
+  setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
+  setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
 
   setMinimumJumpTableEntries(5);
 

diff  --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 290c7b03ea81..5e8acffb6fbc 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -56,6 +56,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
+  Align PrefFunctionAlignment;
+  Align PrefLoopAlignment;
+
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
@@ -95,6 +98,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   }
   bool enableMachineScheduler() const override { return true; }
 
+  Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
+  Align getPrefLoopAlignment() const { return PrefLoopAlignment; }
+
   /// Returns RISCV processor family.
   /// Avoid this function! CPU specifics should be kept local to this class
   /// and preferably modeled with SubtargetFeatures or properties in