[PATCH] D144250: [AMDGPU] Simplify widenScalar condition for BigTy for G_(UN)MERGE_VALUES

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D144250#4134550 <https://reviews.llvm.org/D144250#4134550>, @foad wrote:

> In D144250#4134530 <https://reviews.llvm.org/D144250#4134530>, @arsenm wrote:
>
>> We probably only want 32-bit multiple merge results (except maybe with true16)
>
> AMDGPUInstructionSelector::selectG_UNMERGE_VALUES seems to assume that the source type has a corresponding register class. We certainly don't have register classes for every multiple of 32 up to MaxScalar (currently 1024). How should this work? Should the legalization be guided by exactly which register classes exist?

The point of the legalizer is to match the register classes, which would imply rounding up in the non-existent cases. I was thinking we would eventually just have every multiple of 32 register classes


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