[PATCH] D144250: [AMDGPU] Simplify widenScalar condition for BigTy for G_(UN)MERGE_VALUES

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D144250#4134530 <https://reviews.llvm.org/D144250#4134530>, @arsenm wrote:

> We probably only want 32-bit multiple merge results (except maybe with true16)

AMDGPUInstructionSelector::selectG_UNMERGE_VALUES seems to assume that the source type has a corresponding register class. We certainly don't have register classes for every multiple of 32 up to MaxScalar (currently 1024). How should this work? Should the legalization be guided by exactly which register classes exist?


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https://reviews.llvm.org/D144250