[llvm] df277ec - [X86][MC] Fix the bug of -output-asm-variant=1 for intel syntax

[Shengchen Kan via llvm-commits]

Author: Shengchen Kan
Date: 2023-02-17T09:53:54+08:00
New Revision: df277ec67efd1bec3aa2fa8b02d84db0ea8b2f1c

URL: https://github.com/llvm/llvm-project/commit/df277ec67efd1bec3aa2fa8b02d84db0ea8b2f1c
DIFF: https://github.com/llvm/llvm-project/commit/df277ec67efd1bec3aa2fa8b02d84db0ea8b2f1c.diff

LOG: [X86][MC] Fix the bug of -output-asm-variant=1 for intel syntax

Before this patch

```
$ echo "leal    (,%r15), %eax" | llvm-mc --show-encoding --output-asm-variant=1

        lea     eax, [r15]                      # encoding: [0x42,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00]

$ echo "lea     eax, [r15]" | llvm-mc --show-encoding -x86-asm-syntax=intel --output-asm-variant=1

        lea     eax, [r15]                      # encoding: [0x41,0x8d,0x07]
```

MC printed the register r15 as a base in intel syntax even when it's an index.
Then we got a different encoding by using the assembly from the output of the
first command.

I believe the behavior is too weird to be called a feature.

After this patch, we get

```
$ echo "leal    (,%r15), %eax" | llvm-mc --show-encoding --output-asm-variant=1

        lea     eax, [1*r15]                    # encoding: [0x42,0x8d,0x04,0x3d,0x00,0x00,0x00,0x00]
```

Reviewed By: RKSimon, pengfei, MaskRay

Differential Revision: https://reviews.llvm.org/D144183

Added: 
    

Modified: 
    llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
    llvm/test/MC/Disassembler/X86/intel-syntax.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
index 84da39c4a2952..a8ef195cba78b 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -398,7 +398,7 @@ void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
 
   if (IndexReg.getReg()) {
     if (NeedPlus) O << " + ";
-    if (ScaleVal != 1)
+    if (ScaleVal != 1 || !BaseReg.getReg())
       O << ScaleVal << '*';
     printOperand(MI, Op+X86::AddrIndexReg, O);
     NeedPlus = true;

diff  --git a/llvm/test/MC/Disassembler/X86/intel-syntax.txt b/llvm/test/MC/Disassembler/X86/intel-syntax.txt
index d2f2490c79ea3..c7c0fce268cd2 100644
--- a/llvm/test/MC/Disassembler/X86/intel-syntax.txt
+++ b/llvm/test/MC/Disassembler/X86/intel-syntax.txt
@@ -171,4 +171,11 @@
 # CHECK: lea	rcx, [rsp + 4]
 0x48 0x8d 0x4c 0x24 0x04 
 
+# CHECK: lea	rcx, [1*rax]
+0x48 0x8d 0x0c 0x05 0x00 0x00 0x00 0x00
 
+# CHECK: lea	rcx, [1*rax + 4]
+0x48 0x8d 0x0c 0x05 0x04 0x00 0x00 0x00
+
+# CHECK: lea	rcx, [2*rax]
+0x48 0x8d 0x0c 0x45 0x00 0x00 0x00 0x00