[PATCH] D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:455
+  if (IsWordOp)
+    Inst.addOperand(MCOperand::createImm(3));
+  else
----------------
Inst.addOperand(MCOperand::createImm(IsWordOp ? 3 : 4));


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:9838
+
+      // Check if the offsets match the XTHeadMemPair encoding contraints.
+      if (MemVT == MVT::i32) {
----------------
contraints -> constraints


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td:14
+//===----------------------------------------------------------------------===//
+// T-HEAD C specific DAG Nodes.
+//===----------------------------------------------------------------------===//
----------------
What is "C" here?


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Comment at: llvm/test/CodeGen/RISCV/xtheadmempair.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair -verify-machineinstrs < %s \
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Can we test i64 load/store on rv32 and i128 load on rv64? I assume we use these instructions to handle the split.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D144002/new/

https://reviews.llvm.org/D144002