[PATCH] D144092: [RISCV] Lower interleave and deinterleave intrinsics

[Luke Lau via Phabricator via llvm-commits]

luke updated this revision to Diff 498085.
luke added a comment.

1. Be smarter about generating masks by using generating vmsne.vi vx, 0 directly
2. When SEW < ELEN interleave vectors with vwaddu.vv/vwmacc.vx


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144092/new/

https://reviews.llvm.org/D144092

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
  llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

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