[llvm] 8a17cd9 - AMDGPU: Add a regression test case for D143963

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-02-16T17:11:32Z
New Revision: 8a17cd9905c29f24e7722c41878a536cacbc500b

URL: https://github.com/llvm/llvm-project/commit/8a17cd9905c29f24e7722c41878a536cacbc500b
DIFF: https://github.com/llvm/llvm-project/commit/8a17cd9905c29f24e7722c41878a536cacbc500b.diff

LOG: AMDGPU: Add a regression test case for D143963

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 30177a5834dd..90cb48e08653 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -3417,6 +3417,25 @@ define float @v_fneg_fabs_select_infloop_regression(float %arg, i1 %arg1) {
   ret float %i3
 }
 
+define float @v_fmul_0_fsub_0_infloop_regression(float %arg) {
+; GCN-SAFE-LABEL: v_fmul_0_fsub_0_infloop_regression:
+; GCN-SAFE:       ; %bb.0: ; %bb
+; GCN-SAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-SAFE-NEXT:    v_mul_f32_e32 v0, 0, v0
+; GCN-SAFE-NEXT:    v_sub_f32_e32 v0, 0, v0
+; GCN-SAFE-NEXT:    s_setpc_b64 s[30:31]
+;
+; GCN-NSZ-LABEL: v_fmul_0_fsub_0_infloop_regression:
+; GCN-NSZ:       ; %bb.0: ; %bb
+; GCN-NSZ-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NSZ-NEXT:    v_mul_f32_e32 v0, 0x80000000, v0
+; GCN-NSZ-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  %i = fmul float %arg, 0.0
+  %i1 = fsub float 0.0, %i
+  ret float %i1
+}
+
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 declare float @llvm.fma.f32(float, float, float) #1
 declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)