[llvm] 2ac85cd - [AMDGPU] Regenerate check lines to enable updating for D144050.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 16 08:38:33 PST 2023
Author: Florian Hahn
Date: 2023-02-16T16:38:15Z
New Revision: 2ac85cd563815949f7178e6fba413213ace86709
URL: https://github.com/llvm/llvm-project/commit/2ac85cd563815949f7178e6fba413213ace86709
DIFF: https://github.com/llvm/llvm-project/commit/2ac85cd563815949f7178e6fba413213ace86709.diff
LOG: [AMDGPU] Regenerate check lines to enable updating for D144050.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll b/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
index b3e41b574770b..eaede6b6c4a6a 100644
--- a/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
@@ -1,13 +1,65 @@
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX1010 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX1100 %s
; Test that unused lanes in the s_xor result are masked out with v_cndmask.
-; CHECK-LABEL: combine_add_zext_xor:
-; CHECK: s_xor_b32 [[RESULT:s[0-9]+]]
-; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
-; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
define i32 @combine_add_zext_xor() {
+; GFX1010-LABEL: combine_add_zext_xor:
+; GFX1010: ; %bb.0: ; %.entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: s_branch .LBB0_2
+; GFX1010-NEXT: .LBB0_1: ; %bb9
+; GFX1010-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; GFX1010-NEXT: s_xor_b32 s4, s4, -1
+; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX1010-NEXT: v_add_nc_u32_e32 v2, v1, v0
+; GFX1010-NEXT: v_mov_b32_e32 v1, v2
+; GFX1010-NEXT: s_cbranch_vccz .LBB0_4
+; GFX1010-NEXT: .LBB0_2: ; %.a
+; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1010-NEXT: ; implicit-def: $sgpr4
+; GFX1010-NEXT: s_cbranch_scc1 .LBB0_1
+; GFX1010-NEXT: ; %bb.3: ; %bb
+; GFX1010-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc
+; GFX1010-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s4, 0, v0
+; GFX1010-NEXT: s_branch .LBB0_1
+; GFX1010-NEXT: .LBB0_4: ; %.exit
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: combine_add_zext_xor:
+; GFX1100: ; %bb.0: ; %.entry
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1100-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-NEXT: s_branch .LBB0_2
+; GFX1100-NEXT: .LBB0_1: ; %bb9
+; GFX1100-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: s_xor_b32 s0, s0, -1
+; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_add_nc_u32_e32 v2, v1, v0
+; GFX1100-NEXT: v_mov_b32_e32 v1, v2
+; GFX1100-NEXT: s_cbranch_vccz .LBB0_4
+; GFX1100-NEXT: .LBB0_2: ; %.a
+; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1100-NEXT: ; implicit-def: $sgpr0
+; GFX1100-NEXT: s_cbranch_scc1 .LBB0_1
+; GFX1100-NEXT: ; %bb.3: ; %bb
+; GFX1100-NEXT: ; in Loop: Header=BB0_2 Depth=1
+; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc
+; GFX1100-NEXT: s_waitcnt vmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
+; GFX1100-NEXT: s_branch .LBB0_1
+; GFX1100-NEXT: .LBB0_4: ; %.exit
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
.entry:
br label %.a
@@ -34,12 +86,62 @@ bb9: ; preds = %bb, %.a
; Test that unused lanes in the s_xor result are masked out with v_cndmask.
-; CHECK-LABEL: combine_sub_zext_xor:
-; CHECK: s_xor_b32 [[RESULT:s[0-9]+]]
-; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
-; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
-
define i32 @combine_sub_zext_xor() {
+; GFX1010-LABEL: combine_sub_zext_xor:
+; GFX1010: ; %bb.0: ; %.entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: s_branch .LBB1_2
+; GFX1010-NEXT: .LBB1_1: ; %bb9
+; GFX1010-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; GFX1010-NEXT: s_xor_b32 s4, s4, -1
+; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX1010-NEXT: v_sub_nc_u32_e32 v2, v1, v0
+; GFX1010-NEXT: v_mov_b32_e32 v1, v2
+; GFX1010-NEXT: s_cbranch_vccz .LBB1_4
+; GFX1010-NEXT: .LBB1_2: ; %.a
+; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1010-NEXT: ; implicit-def: $sgpr4
+; GFX1010-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1010-NEXT: ; %bb.3: ; %bb
+; GFX1010-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc
+; GFX1010-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s4, 0, v0
+; GFX1010-NEXT: s_branch .LBB1_1
+; GFX1010-NEXT: .LBB1_4: ; %.exit
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: combine_sub_zext_xor:
+; GFX1100: ; %bb.0: ; %.entry
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1100-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-NEXT: s_branch .LBB1_2
+; GFX1100-NEXT: .LBB1_1: ; %bb9
+; GFX1100-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: s_xor_b32 s0, s0, -1
+; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_sub_nc_u32_e32 v2, v1, v0
+; GFX1100-NEXT: v_mov_b32_e32 v1, v2
+; GFX1100-NEXT: s_cbranch_vccz .LBB1_4
+; GFX1100-NEXT: .LBB1_2: ; %.a
+; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1100-NEXT: ; implicit-def: $sgpr0
+; GFX1100-NEXT: s_cbranch_scc1 .LBB1_1
+; GFX1100-NEXT: ; %bb.3: ; %bb
+; GFX1100-NEXT: ; in Loop: Header=BB1_2 Depth=1
+; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc
+; GFX1100-NEXT: s_waitcnt vmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
+; GFX1100-NEXT: s_branch .LBB1_1
+; GFX1100-NEXT: .LBB1_4: ; %.exit
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
.entry:
br label %.a
@@ -66,12 +168,60 @@ bb9: ; preds = %bb, %.a
; Test that unused lanes in the s_or result are masked out with v_cndmask.
-; CHECK-LABEL: combine_add_zext_or:
-; CHECK: s_or_b32 [[RESULT:s[0-9]+]]
-; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
-; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
-
define i32 @combine_add_zext_or() {
+; GFX1010-LABEL: combine_add_zext_or:
+; GFX1010: ; %bb.0: ; %.entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: s_branch .LBB2_2
+; GFX1010-NEXT: .LBB2_1: ; %bb9
+; GFX1010-NEXT: ; in Loop: Header=BB2_2 Depth=1
+; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1010-NEXT: s_or_b32 s4, s4, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX1010-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX1010-NEXT: s_cbranch_vccz .LBB2_4
+; GFX1010-NEXT: .LBB2_2: ; %.a
+; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1010-NEXT: ; implicit-def: $sgpr4
+; GFX1010-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX1010-NEXT: ; %bb.3: ; %bb
+; GFX1010-NEXT: ; in Loop: Header=BB2_2 Depth=1
+; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc
+; GFX1010-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s4, 0, v0
+; GFX1010-NEXT: s_branch .LBB2_1
+; GFX1010-NEXT: .LBB2_4: ; %.exit
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: combine_add_zext_or:
+; GFX1100: ; %bb.0: ; %.entry
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1100-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-NEXT: s_branch .LBB2_2
+; GFX1100-NEXT: .LBB2_1: ; %bb9
+; GFX1100-NEXT: ; in Loop: Header=BB2_2 Depth=1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1100-NEXT: s_or_b32 s0, s0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX1100-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX1100-NEXT: s_cbranch_vccz .LBB2_4
+; GFX1100-NEXT: .LBB2_2: ; %.a
+; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1100-NEXT: ; implicit-def: $sgpr0
+; GFX1100-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX1100-NEXT: ; %bb.3: ; %bb
+; GFX1100-NEXT: ; in Loop: Header=BB2_2 Depth=1
+; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc
+; GFX1100-NEXT: s_waitcnt vmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
+; GFX1100-NEXT: s_branch .LBB2_1
+; GFX1100-NEXT: .LBB2_4: ; %.exit
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
.entry:
br label %.a
@@ -99,12 +249,60 @@ bb9: ; preds = %bb, %.a
; Test that unused lanes in the s_or result are masked out with v_cndmask.
-; CHECK-LABEL: combine_sub_zext_or:
-; CHECK: s_or_b32 [[RESULT:s[0-9]+]]
-; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
-; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
-
define i32 @combine_sub_zext_or() {
+; GFX1010-LABEL: combine_sub_zext_or:
+; GFX1010: ; %bb.0: ; %.entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: s_branch .LBB3_2
+; GFX1010-NEXT: .LBB3_1: ; %bb9
+; GFX1010-NEXT: ; in Loop: Header=BB3_2 Depth=1
+; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1010-NEXT: s_or_b32 s4, s4, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX1010-NEXT: v_sub_nc_u32_e32 v1, v1, v0
+; GFX1010-NEXT: s_cbranch_vccz .LBB3_4
+; GFX1010-NEXT: .LBB3_2: ; %.a
+; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1010-NEXT: ; implicit-def: $sgpr4
+; GFX1010-NEXT: s_cbranch_scc1 .LBB3_1
+; GFX1010-NEXT: ; %bb.3: ; %bb
+; GFX1010-NEXT: ; in Loop: Header=BB3_2 Depth=1
+; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc
+; GFX1010-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s4, 0, v0
+; GFX1010-NEXT: s_branch .LBB3_1
+; GFX1010-NEXT: .LBB3_4: ; %.exit
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: combine_sub_zext_or:
+; GFX1100: ; %bb.0: ; %.entry
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1100-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-NEXT: s_branch .LBB3_2
+; GFX1100-NEXT: .LBB3_1: ; %bb9
+; GFX1100-NEXT: ; in Loop: Header=BB3_2 Depth=1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1100-NEXT: s_or_b32 s0, s0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX1100-NEXT: v_sub_nc_u32_e32 v1, v1, v0
+; GFX1100-NEXT: s_cbranch_vccz .LBB3_4
+; GFX1100-NEXT: .LBB3_2: ; %.a
+; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1100-NEXT: ; implicit-def: $sgpr0
+; GFX1100-NEXT: s_cbranch_scc1 .LBB3_1
+; GFX1100-NEXT: ; %bb.3: ; %bb
+; GFX1100-NEXT: ; in Loop: Header=BB3_2 Depth=1
+; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc
+; GFX1100-NEXT: s_waitcnt vmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
+; GFX1100-NEXT: s_branch .LBB3_1
+; GFX1100-NEXT: .LBB3_4: ; %.exit
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
.entry:
br label %.a
@@ -132,12 +330,60 @@ bb9: ; preds = %bb, %.a
; Test that unused lanes in the s_and result are masked out with v_cndmask.
-; CHECK-LABEL: combine_add_zext_and:
-; CHECK: s_and_b32 [[RESULT:s[0-9]+]]
-; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
-; CHECK: v_add_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
-
define i32 @combine_add_zext_and() {
+; GFX1010-LABEL: combine_add_zext_and:
+; GFX1010: ; %bb.0: ; %.entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: s_branch .LBB4_2
+; GFX1010-NEXT: .LBB4_1: ; %bb9
+; GFX1010-NEXT: ; in Loop: Header=BB4_2 Depth=1
+; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1010-NEXT: s_and_b32 s4, s4, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX1010-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX1010-NEXT: s_cbranch_vccz .LBB4_4
+; GFX1010-NEXT: .LBB4_2: ; %.a
+; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1010-NEXT: ; implicit-def: $sgpr4
+; GFX1010-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1010-NEXT: ; %bb.3: ; %bb
+; GFX1010-NEXT: ; in Loop: Header=BB4_2 Depth=1
+; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc
+; GFX1010-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s4, 0, v0
+; GFX1010-NEXT: s_branch .LBB4_1
+; GFX1010-NEXT: .LBB4_4: ; %.exit
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: combine_add_zext_and:
+; GFX1100: ; %bb.0: ; %.entry
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1100-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-NEXT: s_branch .LBB4_2
+; GFX1100-NEXT: .LBB4_1: ; %bb9
+; GFX1100-NEXT: ; in Loop: Header=BB4_2 Depth=1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1100-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX1100-NEXT: v_add_nc_u32_e32 v1, v1, v0
+; GFX1100-NEXT: s_cbranch_vccz .LBB4_4
+; GFX1100-NEXT: .LBB4_2: ; %.a
+; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1100-NEXT: ; implicit-def: $sgpr0
+; GFX1100-NEXT: s_cbranch_scc1 .LBB4_1
+; GFX1100-NEXT: ; %bb.3: ; %bb
+; GFX1100-NEXT: ; in Loop: Header=BB4_2 Depth=1
+; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc
+; GFX1100-NEXT: s_waitcnt vmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
+; GFX1100-NEXT: s_branch .LBB4_1
+; GFX1100-NEXT: .LBB4_4: ; %.exit
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
.entry:
br label %.a
@@ -165,12 +411,60 @@ bb9: ; preds = %bb, %.a
; Test that unused lanes in the s_and result are masked out with v_cndmask.
-; CHECK-LABEL: combine_sub_zext_and:
-; CHECK: s_and_b32 [[RESULT:s[0-9]+]]
-; CHECK: v_cndmask_b32_e64 [[ARG:v[0-9]+]], 0, 1, [[RESULT]]
-; CHECK: v_sub_nc_u32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[ARG]]
-
define i32 @combine_sub_zext_and() {
+; GFX1010-LABEL: combine_sub_zext_and:
+; GFX1010: ; %bb.0: ; %.entry
+; GFX1010-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1010-NEXT: v_mov_b32_e32 v1, 0
+; GFX1010-NEXT: s_branch .LBB5_2
+; GFX1010-NEXT: .LBB5_1: ; %bb9
+; GFX1010-NEXT: ; in Loop: Header=BB5_2 Depth=1
+; GFX1010-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1010-NEXT: s_and_b32 s4, s4, vcc_lo
+; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
+; GFX1010-NEXT: v_sub_nc_u32_e32 v1, v1, v0
+; GFX1010-NEXT: s_cbranch_vccz .LBB5_4
+; GFX1010-NEXT: .LBB5_2: ; %.a
+; GFX1010-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1010-NEXT: ; implicit-def: $sgpr4
+; GFX1010-NEXT: s_cbranch_scc1 .LBB5_1
+; GFX1010-NEXT: ; %bb.3: ; %bb
+; GFX1010-NEXT: ; in Loop: Header=BB5_2 Depth=1
+; GFX1010-NEXT: buffer_load_dword v0, v1, s[4:7], 64 offen glc
+; GFX1010-NEXT: s_waitcnt vmcnt(0)
+; GFX1010-NEXT: v_cmp_eq_u32_e64 s4, 0, v0
+; GFX1010-NEXT: s_branch .LBB5_1
+; GFX1010-NEXT: .LBB5_4: ; %.exit
+; GFX1010-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-LABEL: combine_sub_zext_and:
+; GFX1100: ; %bb.0: ; %.entry
+; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX1100-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-NEXT: s_branch .LBB5_2
+; GFX1100-NEXT: .LBB5_1: ; %bb9
+; GFX1100-NEXT: ; in Loop: Header=BB5_2 Depth=1
+; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-NEXT: v_cmp_lt_i32_e32 vcc_lo, 0xfffffbe6, v1
+; GFX1100-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
+; GFX1100-NEXT: v_sub_nc_u32_e32 v1, v1, v0
+; GFX1100-NEXT: s_cbranch_vccz .LBB5_4
+; GFX1100-NEXT: .LBB5_2: ; %.a
+; GFX1100-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1100-NEXT: ; implicit-def: $sgpr0
+; GFX1100-NEXT: s_cbranch_scc1 .LBB5_1
+; GFX1100-NEXT: ; %bb.3: ; %bb
+; GFX1100-NEXT: ; in Loop: Header=BB5_2 Depth=1
+; GFX1100-NEXT: buffer_load_b32 v0, v1, s[0:3], 64 offen glc
+; GFX1100-NEXT: s_waitcnt vmcnt(0)
+; GFX1100-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
+; GFX1100-NEXT: s_branch .LBB5_1
+; GFX1100-NEXT: .LBB5_4: ; %.exit
+; GFX1100-NEXT: s_setpc_b64 s[30:31]
.entry:
br label %.a
@@ -202,3 +496,5 @@ declare i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32>, i32, i32, i32 immarg) #0
attributes #0 = { nounwind readonly willreturn }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; COMMON: {{.*}}
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