[llvm] 1538761 - [LSR] Add test case which shows additional LSR with D144050.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2023-02-16T16:12:07Z
New Revision: 1538761303ce1c06197636602644c85b8c819e04

URL: https://github.com/llvm/llvm-project/commit/1538761303ce1c06197636602644c85b8c819e04
DIFF: https://github.com/llvm/llvm-project/commit/1538761303ce1c06197636602644c85b8c819e04.diff

LOG: [LSR] Add test case which shows additional LSR with D144050.

Added: 
    llvm/test/Transforms/LoopStrengthReduce/lsr-rewrite-to-add-one.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopStrengthReduce/lsr-rewrite-to-add-one.ll b/llvm/test/Transforms/LoopStrengthReduce/lsr-rewrite-to-add-one.ll
new file mode 100644
index 0000000000000..ecbd34732b2b2
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/lsr-rewrite-to-add-one.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=loop-reduce -S %s | FileCheck %s
+
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
+
+define i32 @test(i1 %c.1, ptr %src) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
+; CHECK:       loop.header:
+; CHECK-NEXT:    [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT:    br i1 [[C_1:%.*]], label [[LOOP_LATCH]], label [[LOOP_THEN:%.*]]
+; CHECK:       loop.then:
+; CHECK-NEXT:    [[L:%.*]] = load i32, ptr [[SRC:%.*]], align 4
+; CHECK-NEXT:    [[C_2:%.*]] = icmp eq i32 [[L]], 0
+; CHECK-NEXT:    br label [[LOOP_LATCH]]
+; CHECK:       loop.latch:
+; CHECK-NEXT:    [[P:%.*]] = phi i1 [ [[C_2]], [[LOOP_THEN]] ], [ false, [[LOOP_HEADER]] ]
+; CHECK-NEXT:    [[T:%.*]] = icmp sgt i32 [[IV]], -1050
+; CHECK-NEXT:    [[OR:%.*]] = or i1 [[P]], [[T]]
+; CHECK-NEXT:    [[ZEXT_OR:%.*]] = zext i1 [[OR]] to i32
+; CHECK-NEXT:    [[IV_NEXT]] = add i32 [[IV]], [[ZEXT_OR]]
+; CHECK-NEXT:    [[LOOP_HEADER_TERMCOND:%.*]] = icmp sgt i32 [[IV]], -1050
+; CHECK-NEXT:    br i1 [[LOOP_HEADER_TERMCOND]], label [[LOOP_HEADER]], label [[EXIT:%.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    [[ZEXT_OR_LCSSA:%.*]] = phi i32 [ [[ZEXT_OR]], [[LOOP_LATCH]] ]
+; CHECK-NEXT:    ret i32 [[ZEXT_OR_LCSSA]]
+;
+entry:
+  br label %loop.header
+
+loop.header:
+  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
+  br i1 %c.1, label %loop.latch, label %loop.then
+
+loop.then:
+  %l = load i32, ptr %src
+  %c.2 = icmp eq i32 %l, 0
+  br label %loop.latch
+
+loop.latch:
+  %p = phi i1 [ %c.2, %loop.then ], [ 0, %loop.header ]
+  %t = icmp sgt i32 %iv, -1050
+  %or = or i1 %p, %t
+  %zext.or = zext i1 %or to i32
+  %iv.next = add i32 %iv, %zext.or
+  br i1 %t, label %loop.header, label %exit
+
+exit:
+  ret i32 %zext.or
+}