[llvm] f6fa5a6 - [RISCV][MC] Add support for experimental zfa extension (FLI instruction not included)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 16 08:09:08 PST 2023
Author: Jun Sha (Joshua)
Date: 2023-02-16T08:08:52-08:00
New Revision: f6fa5a66d8a8190002d3eb542e4b5a99deb53004
URL: https://github.com/llvm/llvm-project/commit/f6fa5a66d8a8190002d3eb542e4b5a99deb53004
DIFF: https://github.com/llvm/llvm-project/commit/f6fa5a66d8a8190002d3eb542e4b5a99deb53004.diff
LOG: [RISCV][MC] Add support for experimental zfa extension (FLI instruction not included)
This implements experimental support for the RISCV Zfa extension as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.
This change adds assembly support for all instructions except load-immediate instructions (fli.s/fli.d/fli.h). Assembly support for that instruction and codegen support will follow in separate patches.
Differential Revision: https://reviews.llvm.org/D141984
Added:
llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
llvm/test/MC/RISCV/rv32zfa-only-valid.s
llvm/test/MC/RISCV/zfa-double-invalid.s
llvm/test/MC/RISCV/zfa-half-invalid.s
llvm/test/MC/RISCV/zfa-invalid.s
llvm/test/MC/RISCV/zfa-valid.s
Modified:
llvm/docs/RISCVUsage.rst
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 824270734838..68ca270f05cc 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -154,6 +154,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zcf``
LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_.
+``experimental-zfa``
+ LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). Load-immediate instructions (fli.s/fli.d/fli.h) haven't been implemented yet.
+
``experimental-zihintntl``
LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
@@ -162,7 +165,7 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-zvfh``
LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
-
+
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
Vendor Extensions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index bffd32593a3d..1ff6188e74a0 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -483,6 +483,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
/// Return true if the operand is a valid floating point rounding mode.
bool isFRMArg() const { return Kind == KindTy::FRM; }
+ bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; }
bool isImmXLenLI() const {
int64_t Imm;
@@ -1253,6 +1254,10 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
}
+ case Match_InvalidRTZArg: {
+ SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+ return Error(ErrorLoc, "operand must be 'rtz' floating-point rounding mode");
+ }
case Match_InvalidVTypeI: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3284d8ef4e17..667e0f8359bc 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -131,6 +131,14 @@ def HasStdExtZhinxOrZhinxmin
"'Zhinx' (Half Float in Integer) or "
"'Zhinxmin' (Half Float in Integer Minimal)">;
+def FeatureStdExtZfa
+ : SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
+ "'Zfa' (Additional Floating-Point)",
+ [FeatureStdExtF]>;
+def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
+ AssemblerPredicate<(all_of FeatureStdExtZfa),
+ "'Zfa' (Additional Floating-Point)">;
+
def FeatureStdExtC
: SubtargetFeature<"c", "HasStdExtC", "true",
"'C' (Compressed Instructions)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index dd11ad705696..fe8366a11fc4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1883,6 +1883,7 @@ include "RISCVInstrInfoZb.td"
include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
+include "RISCVInstrInfoZfa.td"
include "RISCVInstrInfoZfh.td"
include "RISCVInstrInfoZicbo.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
new file mode 100644
index 000000000000..91132516d799
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -0,0 +1,99 @@
+//===-- RISCVInstrInfoZfa.td - RISC-V 'Zfa' instructions ---*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zfa'
+// additional floating-point extension, version 0.1.
+// This version is still experimental as the 'Zfa' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RTZArg : AsmOperandClass {
+ let Name = "RTZArg";
+ let RenderMethod = "addFRMArgOperands";
+ let DiagnosticType = "InvalidRTZArg";
+ let ParserMethod = "parseFRMArg";
+}
+
+def rtzarg : Operand<XLenVT> {
+ let ParserMatchClass = RTZArg;
+ let PrintMethod = "printFRMArg";
+ let DecoderMethod = "decodeFRMArg";
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
+class FPBinaryOp_rr<bits<7> funct7, bits<3> funct3, DAGOperand rdty,
+ DAGOperand rsty, string opcodestr>
+ : RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd),
+ (ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
+ UseNamedOperandTable = 1, hasPostISelHook = 1 in
+class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
+ DAGOperand rs1ty, string opcodestr>
+ : RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
+ (ins rs1ty:$rs1, rtzarg:$frm), opcodestr,
+ "$rd, $rs1$frm"> {
+ let rs2 = rs2val;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZfa] in {
+def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, /*Commutable*/ 1>;
+def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, /*Commutable*/ 1>;
+
+def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">;
+def FROUNDNX_S : FPUnaryOp_r_frm<0b0100000, 0b00101, FPR32, FPR32, "froundnx.s">;
+
+def FLTQ_S : FPCmp_rr<0b1010000, 0b101, "fltq.s", FPR32, /*Commutable*/ 1>;
+def FLEQ_S : FPCmp_rr<0b1010000, 0b100, "fleq.s", FPR32, /*Commutable*/ 1>;
+} // Predicates = [HasStdExtZfa]
+
+let Predicates = [HasStdExtZfa, HasStdExtD] in {
+def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, /*Commutable*/ 1>;
+def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, /*Commutable*/ 1>;
+
+def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">;
+def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">;
+
+def FCVTMOD_W_D
+ : FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,
+ Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
+
+def FLTQ_D : FPCmp_rr<0b1010001, 0b101, "fltq.d", FPR64, /*Commutable*/ 1>;
+def FLEQ_D : FPCmp_rr<0b1010001, 0b100, "fleq.d", FPR64, /*Commutable*/ 1>;
+} // Predicates = [HasStdExtZfa, HasStdExtD]
+
+let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
+def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
+ Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
+def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
+ Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
+} // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
+
+let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
+def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, /*Commutable*/ 1>;
+def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, /*Commutable*/ 1>;
+
+def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">;
+def FROUNDNX_H : FPUnaryOp_r_frm<0b0100010, 0b00101, FPR16, FPR16, "froundnx.h">;
+
+def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16, /*Commutable*/ 1>;
+def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16, /*Commutable*/ 1>;
+} // Predicates = [HasStdExtZfa, HasStdExtZfh]
diff --git a/llvm/test/MC/RISCV/rv32zfa-only-valid.s b/llvm/test/MC/RISCV/rv32zfa-only-valid.s
new file mode 100644
index 000000000000..2cf5c1c42f3e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.d a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe2]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fmvh.x.d a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.d.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb2]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fmvp.d.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-double-invalid.s b/llvm/test/MC/RISCV/zfa-double-invalid.s
new file mode 100644
index 000000000000..3a92b18d6b19
--- /dev/null
+++ b/llvm/test/MC/RISCV/zfa-double-invalid.s
@@ -0,0 +1,45 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+zfh \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+zfh \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTD %s
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fminm.d fa0, fa1, fa2
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fmaxm.d fs3, fs4, fs5
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fround.d fs1, fs2
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fround.d fs1, fs2, dyn
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fround.d fs1, fs2, rtz
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fround.d fs1, fs2, rne
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+froundnx.d fs1, fs2
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+froundnx.d fs1, fs2, dyn
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+froundnx.d fs1, fs2, rtz
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+froundnx.d fs1, fs2, rne
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fcvtmod.w.d a1, ft1, rtz
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fltq.d a1, fs1, fs2
+
+# CHECK-NO-EXTD: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}}
+fleq.d a1, ft1, ft2
diff --git a/llvm/test/MC/RISCV/zfa-half-invalid.s b/llvm/test/MC/RISCV/zfa-half-invalid.s
new file mode 100644
index 000000000000..f916c9bd66da
--- /dev/null
+++ b/llvm/test/MC/RISCV/zfa-half-invalid.s
@@ -0,0 +1,42 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXTZFH %s
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fminm.h fa0, fa1, fa2
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fmaxm.h fs3, fs4, fs5
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fround.h fs1, fs2
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fround.h fs1, fs2, dyn
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fround.h fs1, fs2, rtz
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fround.h fs1, fs2, rne
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+froundnx.h fs1, fs2
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+froundnx.h fs1, fs2, dyn
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+froundnx.h fs1, fs2, rtz
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+froundnx.h fs1, fs2, rne
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fltq.h a1, fs1, fs2
+
+# CHECK-NO-EXTZFH: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
+fleq.h a1, ft1, ft2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
new file mode 100644
index 000000000000..067b0317db5d
--- /dev/null
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -0,0 +1,23 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zfa,+d,+zfh < %s 2>&1 | FileCheck -check-prefixes=CHECK-NO-RV64 %s
+
+# Invalid rounding modes
+# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
+# CHECK-NO-RV32: error: operand must be 'rtz' floating-point rounding mode
+fcvtmod.w.d a1, ft1, rne
+
+# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
+# CHECK-NO-RV32: error: operand must be 'rtz' floating-point rounding mode
+fcvtmod.w.d a1, ft1, dyn
+
+# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
+# CHECK-NO-RV32: error: operand must be 'rtz' floating-point rounding mode
+fcvtmod.w.d a1, ft1, rmm
+
+# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
+# CHECK-NO-RV32: error: operand must be 'rtz' floating-point rounding mode
+fcvtmod.w.d a1, ft1, rdn
+
+# CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
+# CHECK-NO-RV32: error: operand must be 'rtz' floating-point rounding mode
+fcvtmod.w.d a1, ft1, rup
diff --git a/llvm/test/MC/RISCV/zfa-valid.s b/llvm/test/MC/RISCV/zfa-valid.s
new file mode 100644
index 000000000000..d67fc81bc35a
--- /dev/null
+++ b/llvm/test/MC/RISCV/zfa-valid.s
@@ -0,0 +1,202 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfa,+d,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfa,+d,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfa,+d,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+d,+zfh \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+d,+zfh \
+# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fminm.s fa0, fa1, fa2
+# CHECK-ASM: encoding: [0x53,0xa5,0xc5,0x28]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fminm.s fa0, fa1, fa2
+
+# CHECK-ASM-AND-OBJ: fmaxm.s fs3, fs4, fs5
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x29]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fmaxm.s fs3, fs4, fs5
+
+# CHECK-ASM-AND-OBJ: fminm.d fa0, fa1, fa2
+# CHECK-ASM: encoding: [0x53,0xa5,0xc5,0x2a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fminm.d fa0, fa1, fa2
+
+# CHECK-ASM-AND-OBJ: fmaxm.d fs3, fs4, fs5
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x2b]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fmaxm.d fs3, fs4, fs5
+
+# CHECK-ASM-AND-OBJ: fminm.h fa0, fa1, fa2
+# CHECK-ASM: encoding: [0x53,0xa5,0xc5,0x2c]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fminm.h fa0, fa1, fa2
+
+# CHECK-ASM-AND-OBJ: fmaxm.h fs3, fs4, fs5
+# CHECK-ASM: encoding: [0xd3,0x39,0x5a,0x2d]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fmaxm.h fs3, fs4, fs5
+
+# CHECK-ASM-AND-OBJ: fround.s fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x49,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.s fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fround.s fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x49,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.s fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: fround.s fs1, fs2, rtz
+# CHECK-ASM: encoding: [0xd3,0x14,0x49,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.s fs1, fs2, rtz
+
+# CHECK-ASM-AND-OBJ: fround.s fs1, fs2, rne
+# CHECK-ASM: encoding: [0xd3,0x04,0x49,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.s fs1, fs2, rne
+
+# CHECK-ASM-AND-OBJ: froundnx.s fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x59,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.s fs1, fs2
+
+# CHECK-ASM-AND-OBJ: froundnx.s fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x59,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.s fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: froundnx.s fs1, fs2, rtz
+# CHECK-ASM: encoding: [0xd3,0x14,0x59,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.s fs1, fs2, rtz
+
+# CHECK-ASM-AND-OBJ: froundnx.s fs1, fs2, rne
+# CHECK-ASM: encoding: [0xd3,0x04,0x59,0x40]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.s fs1, fs2, rne
+
+# CHECK-ASM-AND-OBJ: fround.d fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x49,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.d fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fround.d fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x49,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.d fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: fround.d fs1, fs2, rtz
+# CHECK-ASM: encoding: [0xd3,0x14,0x49,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.d fs1, fs2, rtz
+
+# CHECK-ASM-AND-OBJ: fround.d fs1, fs2, rne
+# CHECK-ASM: encoding: [0xd3,0x04,0x49,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.d fs1, fs2, rne
+
+# CHECK-ASM-AND-OBJ: froundnx.d fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x59,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.d fs1, fs2
+
+# CHECK-ASM-AND-OBJ: froundnx.d fs1, fs2, dyn
+# CHECK-ASM: encoding: [0xd3,0x74,0x59,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.d fs1, fs2, dyn
+
+# CHECK-ASM-AND-OBJ: froundnx.d fs1, fs2, rtz
+# CHECK-ASM: encoding: [0xd3,0x14,0x59,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.d fs1, fs2, rtz
+
+# CHECK-ASM-AND-OBJ: froundnx.d fs1, fs2, rne
+# CHECK-ASM: encoding: [0xd3,0x04,0x59,0x42]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.d fs1, fs2, rne
+
+# CHECK-ASM-AND-OBJ: fround.h ft1, fa1, dyn
+# CHECK-ASM: encoding: [0xd3,0xf0,0x45,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.h ft1, fa1
+
+# CHECK-ASM-AND-OBJ: fround.h ft1, fa1, dyn
+# CHECK-ASM: encoding: [0xd3,0xf0,0x45,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.h ft1, fa1, dyn
+
+# CHECK-ASM-AND-OBJ: fround.h ft1, fa1, rtz
+# CHECK-ASM: encoding: [0xd3,0x90,0x45,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.h ft1, fa1, rtz
+
+# CHECK-ASM-AND-OBJ: fround.h fs1, fs2, rne
+# CHECK-ASM: encoding: [0xd3,0x04,0x49,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fround.h fs1, fs2, rne
+
+# CHECK-ASM-AND-OBJ: froundnx.h ft1, fa1, dyn
+# CHECK-ASM: encoding: [0xd3,0xf0,0x55,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.h ft1, fa1
+
+# CHECK-ASM-AND-OBJ: froundnx.h ft1, fa1, dyn
+# CHECK-ASM: encoding: [0xd3,0xf0,0x55,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.h ft1, fa1, dyn
+
+# CHECK-ASM-AND-OBJ: froundnx.h ft1, fa1, rtz
+# CHECK-ASM: encoding: [0xd3,0x90,0x55,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.h ft1, fa1, rtz
+
+# CHECK-ASM-AND-OBJ: froundnx.h fs1, fs2, rne
+# CHECK-ASM: encoding: [0xd3,0x04,0x59,0x44]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+froundnx.h fs1, fs2, rne
+
+# CHECK-ASM-AND-OBJ: fcvtmod.w.d a1, ft1, rtz
+# CHECK-ASM: encoding: [0xd3,0x95,0x80,0xc2]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fcvtmod.w.d a1, ft1, rtz
+
+# CHECK-ASM-AND-OBJ: fltq.s a1, fs1, fs2
+# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa1]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fltq.s a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.s a1, ft1, ft1
+# CHECK-ASM: encoding: [0xd3,0xc5,0x10,0xa0]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fleq.s a1, ft1, ft1
+
+# CHECK-ASM-AND-OBJ: fltq.d a1, fs1, fs2
+# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa3]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fltq.d a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.d a1, ft1, ft2
+# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa2]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fleq.d a1, ft1, ft2
+
+# CHECK-ASM-AND-OBJ: fltq.h a1, fs1, fs2
+# CHECK-ASM: encoding: [0xd3,0xd5,0x24,0xa5]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fltq.h a1, fs1, fs2
+
+# CHECK-ASM-AND-OBJ: fleq.h a1, ft1, ft2
+# CHECK-ASM: encoding: [0xd3,0xc5,0x20,0xa4]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional Floating-Point){{$}}
+fleq.h a1, ft1, ft2
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