[PATCH] D144183: [X86][MC] Fix the bug of -output-asm-variant=1 for intel syntax
Kan Shengchen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 16 06:27:51 PST 2023
skan updated this revision to Diff 497998.
skan marked an inline comment as done.
skan added a comment.
Address review comments: remove some space
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144183/new/
https://reviews.llvm.org/D144183
Files:
llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
llvm/test/MC/Disassembler/X86/intel-syntax.txt
Index: llvm/test/MC/Disassembler/X86/intel-syntax.txt
===================================================================
--- llvm/test/MC/Disassembler/X86/intel-syntax.txt
+++ llvm/test/MC/Disassembler/X86/intel-syntax.txt
@@ -171,4 +171,5 @@
# CHECK: lea rcx, [rsp + 4]
0x48 0x8d 0x4c 0x24 0x04
-
+# CHECK: lea rcx, [1*rax]
+0x48 0x8d 0x0c 0x05 0x00 0x00 0x00 0x00
Index: llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp
@@ -398,7 +398,7 @@
if (IndexReg.getReg()) {
if (NeedPlus) O << " + ";
- if (ScaleVal != 1)
+ if (ScaleVal != 1 || !BaseReg.getReg())
O << ScaleVal << '*';
printOperand(MI, Op+X86::AddrIndexReg, O);
NeedPlus = true;
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