[PATCH] D144116: [DAGCombiner] Avoid converting (x or/xor const) + y to (x + y) + const if benefit is unclear

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2671
+          // If N0 is a sign mask, it does not introduce add carry.
+          NoAddCarry = Const->getAPIntValue().isSignMask();
+        }
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You might be able to do this as NoAddCarry = isMinSignedConstant(N0.getOperand(1));


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144116/new/

https://reviews.llvm.org/D144116