[PATCH] D143796: [AArch64][ISel] Always use pre-inc/post-inc addressing mode for auto-indexed load/store with constant offset.

[Huihui Zhang via Phabricator via llvm-commits]

huihuiz updated this revision to Diff 497828.
huihuiz retitled this revision from "[SelectionDAG] Negate constant offset before morphing load/store node with pre-dec/post-dec addressing mode." to "[AArch64][ISel] Always use pre-inc/post-inc addressing mode for auto-indexed load/store with constant offset.".
huihuiz edited the summary of this revision.
huihuiz added a comment.
Herald added subscribers: arphaman, kristof.beyls.

Thanks Eli for the feedbacks!

Current AArch64TargetLowering::getIndexedAddressParts() is not splitting out a non-constant offset. If we are to split out a non-constant offset, we need to make sure a negate is applied to that offset.

take another t.ll below , using non-constant offset

  define i8* @test(i8* %ptr, i64 %t0, i64 %off) {
    %t1 = add nuw nsw i64 %t0, %off
    %t2 = mul i64 %t1, -4
    %t3 = getelementptr i8, i8* %ptr, i64 %t2
    %t4 = bitcast i8* %t3 to i32*
    store i32 0, i32* %t4, align 4
    %t5 = shl i64 %t1, 2
    %t6 = sub nuw nsw i64 -8, %t5
    %t7 = getelementptr i8, i8* %ptr, i64 %t6
    %t8 = bitcast i8* %t7 to i32*
    store i32 0, i32* %t8, align 4
    ret i8* %ptr
  }

We are generating

  // %bb.0:
          add     x8, x1, x2
          sub     x8, x0, x8, lsl #2
          str     wzr, [x8]  // We are not splitting out a non-constant offset
          stur    wzr, [x8, #-8]
          ret




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143796/new/

https://reviews.llvm.org/D143796

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll


Index: llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
+
+; Reduced test from https://github.com/llvm/llvm-project/issues/60645.
+; To check that we are generating -32 as offset for the first store.
+
+define i8* @pr60645(i8* %ptr, i64 %t0) {
+; CHECK-LABEL: pr60645:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub x8, x0, x1, lsl #2
+; CHECK-NEXT:    str wzr, [x8, #-32]!
+; CHECK-NEXT:    stur wzr, [x8, #-8]
+; CHECK-NEXT:    ret
+  %t1 = add nuw nsw i64 %t0, 8
+  %t2 = mul i64 %t1, -4
+  %t3 = getelementptr i8, i8* %ptr, i64 %t2
+  %t4 = bitcast i8* %t3 to i32*
+  store i32 0, i32* %t4, align 4
+  %t5 = shl i64 %t1, 2
+  %t6 = sub nuw nsw i64 -8, %t5
+  %t7 = getelementptr i8, i8* %ptr, i64 %t6
+  %t8 = bitcast i8* %t7 to i32*
+  store i32 0, i32* %t8, align 4
+  ret i8* %ptr
+}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -21940,8 +21940,10 @@
       RHSC = -(uint64_t)RHSC;
     if (!isInt<9>(RHSC))
       return false;
-    IsInc = (Op->getOpcode() == ISD::ADD);
-    Offset = Op->getOperand(1);
+    // Always emit pre-inc/post-inc addressing mode. Constant offset is already
+    // negated when dealing with subtraction.
+    IsInc = true;
+    Offset = DAG.getConstant(RHSC, SDLoc(N), RHS->getValueType(0));
     return true;
   }
   return false;


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