[llvm] 08ecef8 - [RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 15 13:03:46 PST 2023
Author: Craig Topper
Date: 2023-02-15T13:03:31-08:00
New Revision: 08ecef8e338f4ccb18bda3f3124a0d92f2512cb2
URL: https://github.com/llvm/llvm-project/commit/08ecef8e338f4ccb18bda3f3124a0d92f2512cb2
DIFF: https://github.com/llvm/llvm-project/commit/08ecef8e338f4ccb18bda3f3124a0d92f2512cb2.diff
LOG: [RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
This matches how they are described in the spec.
Rework the tablegen classes to make this format consistent with
other formats.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D144038
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 666d5c375916..2ec13d141c6e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -44,7 +44,11 @@ enum {
InstFormatCB = 15,
InstFormatCJ = 16,
InstFormatCU = 17,
- InstFormatOther = 18,
+ InstFormatCLB = 18,
+ InstFormatCLH = 19,
+ InstFormatCSB = 20,
+ InstFormatCSH = 21,
+ InstFormatOther = 22,
InstFormatMask = 31,
InstFormatShift = 0,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 8fa16dc19c52..0b692915a509 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -48,7 +48,11 @@ def InstFormatCA : InstFormat<14>;
def InstFormatCB : InstFormat<15>;
def InstFormatCJ : InstFormat<16>;
def InstFormatCU : InstFormat<17>;
-def InstFormatOther : InstFormat<18>;
+def InstFormatCLB : InstFormat<18>;
+def InstFormatCLH : InstFormat<19>;
+def InstFormatCSB : InstFormat<20>;
+def InstFormatCSH : InstFormat<21>;
+def InstFormatOther : InstFormat<22>;
class RISCVVConstraint<bits<3> val> {
bits<3> Value = val;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 602d730508d0..fa1c3e916412 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -168,3 +168,65 @@ class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
let Inst{6-2} = funct5;
let Inst{1-0} = opcode;
}
+
+// The immediate value encoding
diff ers for each instruction, so each subclass
+// is responsible for setting the appropriate bits in the Inst field.
+// The bits Inst{6-5} must be set for each instruction.
+class RVInst16CLB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLB> {
+ bits<3> rd;
+ bits<3> rs1;
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rs1;
+ let Inst{4-2} = rd;
+ let Inst{1-0} = opcode;
+}
+
+// The immediate value encoding
diff ers for each instruction, so each subclass
+// is responsible for setting the appropriate bits in the Inst field.
+// The bits Inst{5} must be set for each instruction.
+class RVInst16CLH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLH> {
+ bits<3> rd;
+ bits<3> rs1;
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rs1;
+ let Inst{6} = funct1;
+ let Inst{4-2} = rd;
+ let Inst{1-0} = opcode;
+}
+
+// The immediate value encoding
diff ers for each instruction, so each subclass
+// is responsible for setting the appropriate bits in the Inst field.
+// The bits Inst{6-5} must be set for each instruction.
+class RVInst16CSB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSB> {
+ bits<3> rs2;
+ bits<3> rs1;
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rs1;
+ let Inst{4-2} = rs2;
+ let Inst{1-0} = opcode;
+}
+
+// The immediate value encoding
diff ers for each instruction, so each subclass
+// is responsible for setting the appropriate bits in the Inst field.
+// The bits Inst{5} must be set for each instruction.
+class RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSH> {
+ bits<3> rs2;
+ bits<3> rs1;
+
+ let Inst{15-10} = funct6;
+ let Inst{9-7} = rs1;
+ let Inst{6} = funct1;
+ let Inst{4-2} = rs2;
+ let Inst{1-0} = opcode;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index e9983ee3a38e..f43c180886cd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -36,6 +36,46 @@ def uimm2_lsb0 : Operand<XLenVT>,
// Instruction Class Templates
//===----------------------------------------------------------------------===//
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class CLoadB_ri<bits<6> funct6, string OpcodeStr>
+ : RVInst16CLB<funct6, 0b00, (outs GPRC:$rd),
+ (ins GPRCMem:$rs1, uimm2:$imm),
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<2> imm;
+
+ let Inst{6-5} = imm{0,1};
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class CLoadH_ri<bits<6> funct6, bit funct1, string OpcodeStr>
+ : RVInst16CLH<funct6, funct1, 0b00, (outs GPRC:$rd),
+ (ins GPRCMem:$rs1, uimm2_lsb0:$imm),
+ OpcodeStr, "$rd, ${imm}(${rs1})"> {
+ bits<2> imm;
+
+ let Inst{5} = imm{1};
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class CStoreB_rri<bits<6> funct6, string OpcodeStr>
+ : RVInst16CSB<funct6, 0b00, (outs),
+ (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bits<2> imm;
+
+ let Inst{6-5} = imm{0,1};
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class CStoreH_rri<bits<6> funct6, bit funct1, string OpcodeStr>
+ : RVInst16CSH<funct6, funct1, 0b00, (outs),
+ (ins GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
+ OpcodeStr, "$rs2, ${imm}(${rs1})"> {
+ bits<2> imm;
+
+ let Inst{5} = imm{1};
+}
+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
RVInst16CU<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
@@ -72,48 +112,17 @@ let Predicates = [HasStdExtZcb] in {
def C_NOT : RVZcArith_r<0b11101 , "c.not">,
Sched<[WriteIALU, ReadIALU]>;
-def C_LBU : CLoad_ri<0b100, "c.lbu", GPRC, uimm2>,
- Sched<[WriteLDB, ReadMemBase]> {
- bits<2> imm;
-
- let Inst{12-10} = 0b000;
- let Inst{6-5} = imm{0,1};
-}
-
-def C_LHU : CLoad_ri<0b100, "c.lhu", GPRC, uimm2_lsb0>,
- Sched<[WriteLDH, ReadMemBase]> {
- bits<2> imm;
-
- let Inst{12-10} = 0b001;
- let Inst{6} = 0b0;
- let Inst{5} = imm{1};
-}
-
-def C_LH : CLoad_ri<0b100, "c.lh", GPRC, uimm2_lsb0>,
- Sched<[WriteLDH, ReadMemBase]> {
- bits<2> imm;
-
- let Inst{12-10} = 0b001;
- let Inst{6} = 0b1;
- let Inst{5} = imm{1};
-}
-
-def C_SB : CStore_rri<0b100, "c.sb", GPRC, uimm2>,
- Sched<[WriteSTB, ReadStoreData, ReadMemBase]> {
- bits<2> imm;
-
- let Inst{12-10} = 0b010;
- let Inst{6-5} = imm{0,1};
-}
-
-def C_SH : CStore_rri<0b100, "c.sh", GPRC, uimm2_lsb0>,
- Sched<[WriteSTH, ReadStoreData, ReadMemBase]> {
- bits<2> imm;
-
- let Inst{12-10} = 0b011;
- let Inst{6} = 0b1;
- let Inst{5} = imm{1};
-}
+def C_LBU : CLoadB_ri<0b100000, "c.lbu">,
+ Sched<[WriteLDB, ReadMemBase]>;
+def C_LHU : CLoadH_ri<0b100001, 0b0, "c.lhu">,
+ Sched<[WriteLDH, ReadMemBase]>;
+def C_LH : CLoadH_ri<0b100001, 0b1, "c.lh">,
+ Sched<[WriteLDH, ReadMemBase]>;
+
+def C_SB : CStoreB_rri<0b100010, "c.sb">,
+ Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+def C_SH : CStoreH_rri<0b100011, 0b1, "c.sh">,
+ Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
}
let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
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