[PATCH] D141924: [IR] Add new intrinsics interleave and deinterleave vectors

[Caroline via Phabricator via llvm-commits]

CarolineConcatto marked 2 inline comments as done.
CarolineConcatto added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:11569
+  SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
+                           DAG.getConstant(0, DL, MVT::i64));
+  SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
----------------
paulwalker-arm wrote:
> It's better to use `getVectorIdxConstant` here.
Thank you Paul,
I did not know about this function.


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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:11569
+  SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
+                           DAG.getConstant(0, DL, MVT::i64));
+  SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, InVec,
----------------
luke wrote:
> CarolineConcatto wrote:
> > paulwalker-arm wrote:
> > > It's better to use `getVectorIdxConstant` here.
> > Thank you Paul,
> > I did not know about this function.
> Seconded, I'm working on a patch to lower these intrinsics to RISC-V and it currently throws an assertion here on RV32 as it doesn't support MVT::i64 constants. 
@luke Does it solved your problem if we replace by getVectorIdxConstant like suggest by Paul?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141924/new/

https://reviews.llvm.org/D141924