[PATCH] D144033: [AMDGPU][MC][GFX11] Add partial NSA format for image sample instructions

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:908-913
+        if (isGFX11Plus())
+          PartialNSA = true;
+        else
+          // The NSA encoding does not contain enough operands for the
+          // combination of base opcode / dimension. Should this be an error?
+          return MCDisassembler::Success;
----------------



================
Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:957
+  // For GFX11 vaddr4 provides all additional components in sequential VGPRs if
+  // more then 5 vaddrs are needed.
+  int16_t VAddrSAOp =
----------------
"more th**a**n"


================
Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:974
                                         &MRI.getRegClass(AddrRCID));
-    if (NewVAddr0 == AMDGPU::NoRegister)
+    if (NewVAddrSA == AMDGPU::NoRegister)
       return MCDisassembler::Success;
----------------



================
Comment at: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:989
 
-  if (NewVAddr0 != AMDGPU::NoRegister) {
-    MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
+  if (NewVAddrSA != AMDGPU::NoRegister) {
+    MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA);
----------------



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D144033/new/

https://reviews.llvm.org/D144033