[PATCH] D144091: [RISCV][NFC] Add VIOTA_VL node

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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This adds a node for the viota.m instruction so that it can be used
during instruction lowering.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144091

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td


Index: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -243,6 +243,14 @@
                                                  SDTCisSameNumEltsAs<1, 2>,
                                                  SDTCisVT<3, XLenVT>]>>;
 
+def riscv_viota_vl : SDNode<"RISCVISD::VIOTA_VL",
+                           SDTypeProfile<1, 4, [SDTCisVec<0>,
+                                                SDTCisSameAs<1, 0>,
+                                                SDTCisSameNumEltsAs<0, 2>,
+                                                SDTCVecEltisVT<2, i1>,
+                                                SDTCisSameAs<2, 3>,
+                                                SDTCisVT<4, XLenVT>]>>;
+
 def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>,
                                                SDTCisSameNumEltsAs<0, 1>,
                                                SDTCisSameNumEltsAs<1, 2>,
@@ -1883,7 +1891,7 @@
             (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX)
                  VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>;
 
-  // Match the not idiom to the vmnot.m pseudo.
+  // Match the not idiom to the vmnand.m pseudo.
   def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)),
             (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX)
                  VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>;
@@ -1909,6 +1917,17 @@
                  VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
 }
 
+// 15.8 viota.m
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (riscv_viota_vl vti.RegClass:$merge,
+                                        (vti.Mask VR:$rs2),
+                                        (vti.Mask V0),
+                                        VLOpFrag)),
+            (!cast<Instruction>("PseudoVIOTA_M_"#vti.LMul.MX#_#"MASK")
+                vti.RegClass:$merge, (vti.Mask VR:$rs2), (vti.Mask V0),
+                GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
+}
+
 } // Predicates = [HasVInstructions]
 
 // 16. Vector Permutation Instructions
Index: llvm/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -291,6 +291,10 @@
   VMCLR_VL,
   VMSET_VL,
 
+  // viota.m with additional mask and VL operands.
+  // Operands are (passthru, src, mask, vl)
+  VIOTA_VL,
+
   // Matches the semantics of vrgather.vx and vrgather.vv with extra operands
   // for passthru and VL. Operands are (src, index, mask, passthru, vl).
   VRGATHER_VX_VL,
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13305,6 +13305,7 @@
   NODE_NAME_CASE(VMXOR_VL)
   NODE_NAME_CASE(VMCLR_VL)
   NODE_NAME_CASE(VMSET_VL)
+  NODE_NAME_CASE(VIOTA_VL)
   NODE_NAME_CASE(VRGATHER_VX_VL)
   NODE_NAME_CASE(VRGATHER_VV_VL)
   NODE_NAME_CASE(VRGATHEREI16_VV_VL)


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