[PATCH] D144086: [AArch64] Load into zero vector patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, bipmis, david-arm, t.p.northover.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

A LDR will implicitly zero the rest of the vector, so `vector_insert(zeros, load, 0)` can use a single load. This adds tablegen patterns for both scaled and unscaled loads, detecting where we are inserting a load into the lower element of a zero vector.


https://reviews.llvm.org/D144086

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/load-insert-zero.ll
  llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll

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