[PATCH] D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
Philipp Tomsich via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 14 14:49:17 PST 2023
philipp.tomsich added inline comments.
================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2665
+ SMLoc Loc = Operands[1]->getStartLoc();
+ return Error(Loc, "The source register and destination registers "
+ "cannot be equal.");
----------------
craig.topper wrote:
> philipp.tomsich wrote:
> > craig.topper wrote:
> > > Does this restrict apply for TH_SDD/TH_SWD? I don't see it in the spec.
> > Given that QEMU had this constraint, but it was missing in the spec, I checked on an Allwinner D1.
> > Turns out that LDD works with with $rs1 == $rs2 and with $rs1 == $rs2 == $rd.
> Did you mean SDD instead of LDD?
Yes, the store instructions (SDD and SWD) work.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144002/new/
https://reviews.llvm.org/D144002
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