[PATCH] D144002: [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 14 14:37:57 PST 2023
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2672
+ // The last operand must be constant 3 or 4 depending on the data width.
+ if (IsWordOp && Inst.getOperand(4).getImm() != 3) {
+ SMLoc Loc = Operands.back()->getStartLoc();
----------------
Why does this 3rd operand exist at all?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D144002/new/
https://reviews.llvm.org/D144002
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