[PATCH] D144012: [SPARC][MC] Fix encoding of backwards BPr branches

[Koakuma via Phabricator via llvm-commits]

koakuma created this revision.
koakuma added reviewers: arsenm, jrtc27, dcederman, brad, ro, MaskRay.
Herald added subscribers: fedor.sergeev, hiraditya, jyknight.
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Make sure that the upper bits of the offset is placed in bits 20-21 of the instruction word.
This fixes the encoding of backwards (negative offset) BPr branches.

(Previously, the upper two bits of the offset would overwrite parts of the rs1 field, causing it to branch on the wrong register, with the wrong offset)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144012

Files:
  llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
  llvm/test/MC/Sparc/sparc64-bpr-offset.s


Index: llvm/test/MC/Sparc/sparc64-bpr-offset.s
===================================================================
--- /dev/null
+++ llvm/test/MC/Sparc/sparc64-bpr-offset.s
@@ -0,0 +1,31 @@
+! RUN: llvm-mc -arch=sparcv9 -filetype=obj %s | llvm-objdump -d - | FileCheck %s --check-prefix=BIN
+
+        !! SPARCv9/SPARC64 BPr branches have different offset encoding than the others,
+        !! so make sure that our offset bits don't trample on other fields.
+        !! This is particularly important with backwards branches.
+
+        ! BIN:  0: 02 c8 40 01  	brz %g1, 1
+        ! BIN:  4: 04 c8 40 01  	brlez %g1, 1
+        ! BIN:  8: 06 c8 40 01  	brlz %g1, 1
+        ! BIN:  c: 0a c8 40 01  	brnz %g1, 1
+        ! BIN: 10: 0c c8 40 01  	brgz %g1, 1
+        ! BIN: 14: 0e c8 40 01  	brgez %g1, 1
+        brz   %g1, .+4
+        brlez %g1, .+4
+        brlz  %g1, .+4
+        brnz  %g1, .+4
+        brgz  %g1, .+4
+        brgez %g1, .+4
+
+        ! BIN: 18: 02 f8 7f ff  	brz %g1, 65535
+        ! BIN: 1c: 04 f8 7f ff  	brlez %g1, 65535
+        ! BIN: 20: 06 f8 7f ff  	brlz %g1, 65535
+        ! BIN: 24: 0a f8 7f ff  	brnz %g1, 65535
+        ! BIN: 28: 0c f8 7f ff  	brgz %g1, 65535
+        ! BIN: 2c: 0e f8 7f ff  	brgez %g1, 65535
+        brz   %g1, .-4
+        brlez %g1, .-4
+        brlz  %g1, .-4
+        brnz  %g1, .-4
+        brgz  %g1, .-4
+        brgez %g1, .-4
Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
===================================================================
--- llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
+++ llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
@@ -62,6 +62,9 @@
     case Sparc::fixup_sparc_call30:  return ELF::R_SPARC_WDISP30;
     case Sparc::fixup_sparc_br22:    return ELF::R_SPARC_WDISP22;
     case Sparc::fixup_sparc_br19:    return ELF::R_SPARC_WDISP19;
+    case Sparc::fixup_sparc_br16_14:
+    case Sparc::fixup_sparc_br16_2:
+      return ELF::R_SPARC_WDISP16;
     case Sparc::fixup_sparc_pc22:    return ELF::R_SPARC_PC22;
     case Sparc::fixup_sparc_pc10:    return ELF::R_SPARC_PC10;
     case Sparc::fixup_sparc_wplt30:  return ELF::R_SPARC_WPLT30;
Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
===================================================================
--- llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+++ llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
@@ -42,7 +42,7 @@
     return (Value >> 2) & 0x7ffff;
 
   case Sparc::fixup_sparc_br16_2:
-    return (Value >> 2) & 0xc000;
+    return ((Value >> 2) & 0xc000) << 6;
 
   case Sparc::fixup_sparc_br16_14:
     return (Value >> 2) & 0x3fff;


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