[PATCH] D143988: [AArch64] Always lower fp16 zero to FMOVH0

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, jaykang10, david-arm, bipmis.
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We can always use `FMOVH0` to lower fp16 zero, even without fullfp16. We can either expand it to `movi d0, #0` or `fmov s0, wzr`, which will both clear all the bits of the register.


https://reviews.llvm.org/D143988

Files:
  llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/arm64-fmax.ll
  llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
  llvm/test/CodeGen/AArch64/f16-imm.ll
  llvm/test/CodeGen/AArch64/fp16-vector-nvcast.ll
  llvm/test/CodeGen/AArch64/mattr-all.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd.ll

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