[PATCH] D134599: [RISCV] Add CodeGen support of RISCV zcmp Extension
KaiYi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 14 00:19:47 PST 2023
KYG added inline comments.
Herald added a subscriber: luke.
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Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:268
+ Register Reg = Entry.getReg();
+ if (!(Reg == RISCV::X26 || RISCV::PGPRRegClass.contains(Reg))) {
+ NonePushStackOffset -= MFI.getObjectSize(Entry.getFrameIdx());
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Seems like the `def PGPR : RegisterClass ...` is missed in RISCVRegisterInfo.td?
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Comment at: llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp:105
+ MachineInstr &MI = *I;
+ if (auto OperandPair = TII->isLoadImmImpl(MI)) {
+ Register DestReg = OperandPair->Destination->getReg();
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Um...where is the implementation of this function? (Or use `isCopyInstrImpl()` instead?)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D134599/new/
https://reviews.llvm.org/D134599
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