[llvm] 4f0eb57 - AMDGPU: Teach getNegatedExpression about rcp

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Tue Feb 14 00:02:49 PST 2023


Author: Matt Arsenault
Date: 2023-02-14T04:02:39-04:00
New Revision: 4f0eb57222deae1df329539e8179bc95d4f4df6d

URL: https://github.com/llvm/llvm-project/commit/4f0eb57222deae1df329539e8179bc95d4f4df6d
DIFF: https://github.com/llvm/llvm-project/commit/4f0eb57222deae1df329539e8179bc95d4f4df6d.diff

LOG: AMDGPU: Teach getNegatedExpression about rcp

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 07ce48bfac5a2..aa5d2b951ff8c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -800,6 +800,17 @@ SDValue AMDGPUTargetLowering::getNegatedExpression(
       return SDValue();
     break;
   }
+  case AMDGPUISD::RCP: {
+    SDValue Src = Op.getOperand(0);
+    EVT VT = Op.getValueType();
+    SDLoc SL(Op);
+
+    SDValue NegSrc = getNegatedExpression(Src, DAG, LegalOperations,
+                                          ForCodeSize, Cost, Depth);
+    if (NegSrc)
+      return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags());
+    return SDValue();
+  }
   default:
     break;
   }

diff  --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
index 610110706a121..30177a5834dd3 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll
@@ -2030,9 +2030,9 @@ define float @v_negated_rcp_f32(float %arg0, float %arg1) #1 {
 ; GCN-LABEL: v_negated_rcp_f32:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_fma_f32 v0, -v0, v1, -2.0
+; GCN-NEXT:    v_fma_f32 v0, v0, v1, 2.0
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    v_sub_f32_e32 v0, v1, v0
+; GCN-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %neg.arg0 = fneg float %arg0
   %fma = call nsz float @llvm.fma.f32(float %neg.arg0, float %arg1, float -2.0)


        


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