[llvm] 5e78b74 - [ARM] Use llvm::rotl and llvm::rotr (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 13 21:28:56 PST 2023
Author: Kazu Hirata
Date: 2023-02-13T21:28:50-08:00
New Revision: 5e78b749eccf0aa57433b177103420103d4e13ec
URL: https://github.com/llvm/llvm-project/commit/5e78b749eccf0aa57433b177103420103d4e13ec
DIFF: https://github.com/llvm/llvm-project/commit/5e78b749eccf0aa57433b177103420103d4e13ec.diff
LOG: [ARM] Use llvm::rotl and llvm::rotr (NFC)
Added:
Modified:
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index f1ba0154b274f..1cf6de7585ee5 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2499,7 +2499,7 @@ void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
while (NumBytes) {
unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
- unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
+ unsigned ThisVal = NumBytes & llvm::rotr<uint32_t>(0xFF, RotAmt);
assert(ThisVal && "Didn't extract field correctly");
// We will handle these bits from offset, clear them.
@@ -2680,7 +2680,7 @@ bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
// Otherwise, pull as much of the immedidate into this ADDri/SUBri
// as possible.
unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
- unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
+ unsigned ThisImmVal = Offset & llvm::rotr<uint32_t>(0xFF, RotAmt);
// We will handle these bits from offset, clear them.
Offset &= ~ThisImmVal;
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 2586dd4cb3544..75733a9287805 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8798,7 +8798,7 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
// before passing it to the ADR instruction.
unsigned Enc = Inst.getOperand(2).getImm();
TmpInst.addOperand(MCOperand::createImm(
- ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
+ llvm::rotr<uint32_t>(Enc & 0xFF, (Enc & 0xF00) >> 7)));
} else {
// Turn PC-relative expression into absolute expression.
// Reading PC provides the start of the current instruction + 8 and
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 597eba23b6012..38c291cf82101 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4910,7 +4910,7 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
} else {
unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
unsigned rot = fieldFromInstruction(Val, 7, 5);
- unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
+ unsigned imm = llvm::rotr<uint32_t>(unrot, rot);
Inst.addOperand(MCOperand::createImm(imm));
}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
index 3170d2a1284fb..163360c08ffba 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
@@ -81,20 +81,6 @@ namespace ARM_AM {
}
}
- /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
- ///
- inline unsigned rotr32(unsigned Val, unsigned Amt) {
- assert(Amt < 32 && "Invalid rotate amount");
- return (Val >> Amt) | (Val << ((32-Amt)&31));
- }
-
- /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
- ///
- inline unsigned rotl32(unsigned Val, unsigned Amt) {
- assert(Amt < 32 && "Invalid rotate amount");
- return (Val << Amt) | (Val >> ((32-Amt)&31));
- }
-
//===--------------------------------------------------------------------===//
// Addressing Mode #1: shift_operand with registers
//===--------------------------------------------------------------------===//
@@ -139,7 +125,7 @@ namespace ARM_AM {
unsigned RotAmt = TZ & ~1;
// If we can handle this spread, return it.
- if ((rotr32(Imm, RotAmt) & ~255U) == 0)
+ if ((llvm::rotr<uint32_t>(Imm, RotAmt) & ~255U) == 0)
return (32-RotAmt)&31; // HW rotates right, not left.
// For values like 0xF000000F, we should ignore the low 6 bits, then
@@ -147,7 +133,7 @@ namespace ARM_AM {
if (Imm & 63U) {
unsigned TZ2 = llvm::countr_zero(Imm & ~63U);
unsigned RotAmt2 = TZ2 & ~1;
- if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
+ if ((llvm::rotr<uint32_t>(Imm, RotAmt2) & ~255U) == 0)
return (32-RotAmt2)&31; // HW rotates right, not left.
}
@@ -168,40 +154,40 @@ namespace ARM_AM {
unsigned RotAmt = getSOImmValRotate(Arg);
// If this cannot be handled with a single shifter_op, bail out.
- if (rotr32(~255U, RotAmt) & Arg)
+ if (llvm::rotr<uint32_t>(~255U, RotAmt) & Arg)
return -1;
// Encode this correctly.
- return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
+ return llvm::rotl<uint32_t>(Arg, RotAmt) | ((RotAmt >> 1) << 8);
}
/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
/// or'ing together two SOImmVal's.
inline bool isSOImmTwoPartVal(unsigned V) {
// If this can be handled with a single shifter_op, bail out.
- V = rotr32(~255U, getSOImmValRotate(V)) & V;
+ V = llvm::rotr<uint32_t>(~255U, getSOImmValRotate(V)) & V;
if (V == 0)
return false;
// If this can be handled with two shifter_op's, accept.
- V = rotr32(~255U, getSOImmValRotate(V)) & V;
+ V = llvm::rotr<uint32_t>(~255U, getSOImmValRotate(V)) & V;
return V == 0;
}
/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
/// return the first chunk of it.
inline unsigned getSOImmTwoPartFirst(unsigned V) {
- return rotr32(255U, getSOImmValRotate(V)) & V;
+ return llvm::rotr<uint32_t>(255U, getSOImmValRotate(V)) & V;
}
/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
/// return the second chunk of it.
inline unsigned getSOImmTwoPartSecond(unsigned V) {
// Mask out the first hunk.
- V = rotr32(~255U, getSOImmValRotate(V)) & V;
+ V = llvm::rotr<uint32_t>(~255U, getSOImmValRotate(V)) & V;
// Take what's left.
- assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
+ assert(V == (llvm::rotr<uint32_t>(255U, getSOImmValRotate(V)) & V));
return V;
}
@@ -216,7 +202,7 @@ namespace ARM_AM {
// Return false if ~(-First) is not a SoImmval.
First = getSOImmTwoPartFirst(-V);
First = ~(-First);
- return !(rotr32(~255U, getSOImmValRotate(First)) & First);
+ return !(llvm::rotr<uint32_t>(~255U, getSOImmValRotate(First)) & First);
}
/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
@@ -307,8 +293,9 @@ namespace ARM_AM {
return -1;
// If 'Arg' can be handled with a single shifter_op return the value.
- if ((rotr32(0xff000000U, RotAmt) & V) == V)
- return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
+ if ((llvm::rotr<uint32_t>(0xff000000U, RotAmt) & V) == V)
+ return (llvm::rotr<uint32_t>(V, 24 - RotAmt) & 0x7f) |
+ ((RotAmt + 8) << 7);
return -1;
}
@@ -345,7 +332,7 @@ namespace ARM_AM {
// out. Those should be handled directly, not with a two-part val.
if (getT2SOImmValSplatVal(V) != -1)
return false;
- V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+ V = llvm::rotr<uint32_t>(~255U, getT2SOImmValRotate(V)) & V;
if (V == 0)
return false;
@@ -369,7 +356,7 @@ namespace ARM_AM {
assert (isT2SOImmTwoPartVal(Imm) &&
"Immedate cannot be encoded as two part immediate!");
// Try a shifter operand as one part
- unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
+ unsigned V = llvm::rotr<uint32_t>(~255, getT2SOImmValRotate(Imm)) & Imm;
// If the rest is encodable as an immediate, then return it.
if (getT2SOImmVal(V) != -1) return V;
@@ -759,4 +746,3 @@ namespace ARM_AM {
} // end namespace llvm
#endif
-
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
index 1ada656d72eff..737c373b14335 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
@@ -1386,7 +1386,7 @@ void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
break;
}
- int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
+ int32_t Rotated = llvm::rotr<uint32_t>(Bits, Rot);
if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
// #rot has the least possible value
O << "#" << markup("<imm:");
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 1a5370e798657..2ea0eaa0aad8f 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -399,7 +399,7 @@ void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
// Use one T2 instruction to reduce NumBytes
// FIXME: Move this to ARMAddressingModes.h?
unsigned RotAmt = llvm::countl_zero(ThisVal);
- ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
+ ThisVal = ThisVal & llvm::rotr<uint32_t>(0xff000000U, RotAmt);
NumBytes &= ~ThisVal;
assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
"Bit extraction didn't work?");
@@ -604,7 +604,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
// Otherwise, extract 8 adjacent bits from the immediate into this
// t2ADDri/t2SUBri.
unsigned RotAmt = llvm::countl_zero<unsigned>(Offset);
- unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
+ unsigned ThisImmVal = Offset & llvm::rotr<uint32_t>(0xff000000U, RotAmt);
// We will handle these bits from offset, clear them.
Offset &= ~ThisImmVal;
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