[llvm] a411bc7 - [RISCV] Rename InstFormatCSZN->InstFormatCU to match latest Zcb spec. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-02-13T21:14:03-08:00
New Revision: a411bc72742695b9c9fcd772295753e3b7a952e2

URL: https://github.com/llvm/llvm-project/commit/a411bc72742695b9c9fcd772295753e3b7a952e2
DIFF: https://github.com/llvm/llvm-project/commit/a411bc72742695b9c9fcd772295753e3b7a952e2.diff

LOG: [RISCV] Rename InstFormatCSZN->InstFormatCU to match latest Zcb spec. NFC

This was updated in version 1.0.2 of the spec. Latest version
https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3/Zc-v1.0.3.pdf

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    llvm/lib/Target/RISCV/RISCVInstrFormats.td
    llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
    llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 005dac5d13ed..a3aa82e71f8e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -43,7 +43,7 @@ enum {
   InstFormatCA = 14,
   InstFormatCB = 15,
   InstFormatCJ = 16,
-  InstFormatCSZN = 17,
+  InstFormatCU = 17,
   InstFormatOther = 18,
 
   InstFormatMask = 31,

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 5105e9fd7722..8fa16dc19c52 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -47,7 +47,7 @@ def InstFormatCS     : InstFormat<13>;
 def InstFormatCA     : InstFormat<14>;
 def InstFormatCB     : InstFormat<15>;
 def InstFormatCJ     : InstFormat<16>;
-def InstFormatCSZN   : InstFormat<17>;
+def InstFormatCU     : InstFormat<17>;
 def InstFormatOther  : InstFormat<18>;
 
 class RISCVVConstraint<bits<3> val> {

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index f3da5ef22038..602d730508d0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -158,9 +158,9 @@ class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
   let Inst{1-0} = opcode;
 }
 
-class RVInst16CSZN<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
-                   dag ins, string opcodestr, string argstr>
-    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSZN>{
+class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
+                 dag ins, string opcodestr, string argstr>
+    : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCU>{
   bits<3> rd;
 
   let Inst{15-10} = funct6;

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 564b02fdeb14..e9983ee3a38e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -38,8 +38,8 @@ def uimm2_lsb0 : Operand<XLenVT>,
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVZcArith_r<bits<5> funct5, string OpcodeStr> :
-  RVInst16CSZN<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
-               OpcodeStr, "$rd"> {
+  RVInst16CU<0b100111, funct5, 0b01, (outs GPRC:$rd_wb), (ins GPRC:$rd),
+             OpcodeStr, "$rd"> {
   let Constraints = "$rd = $rd_wb";
 }