[PATCH] D143953: [RISCV] Accept zicsr and zifencei command line options

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D143953#4124649 <https://reviews.llvm.org/D143953#4124649>, @jrtc27 wrote:

> In D143953#4124636 <https://reviews.llvm.org/D143953#4124636>, @reames wrote:
>
>> @jrtc27 Not sure if this changes your take, but I realized the variant being introduced is maybe much less interesting than I'd first thought.  We generally make no effort to make sure an extension was defined in the spec version corresponding to our base revision.  Given that, we have a bunch of cases where we allow I2.0 + some random extension.  Given that, this one stops looking all that interesting.  It doesn't actually set much precedent - because we already did that, a long time ago.
>>
>> If you agree with that framing, I'll rework the description.
>
> Hm, do we allow M + Zmmul? If so then I guess I can get behind that view.



  $ ~/llvm-dev/build/bin/clang -target riscv64 -march=rv64g_zmmul vector_add_i32.c -S
  $ cat vector_add_i32.s 
  	.text
  	.attribute	4, 16
  	.attribute	5, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_zmmul1p0"

vector_add_i32.c is a random C file; contents are uninteresting.


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https://reviews.llvm.org/D143953