[PATCH] D142109: [LoopVectorize] Remove runtime check and scalar tail loop when tail-folding.

[Florian Hahn via Phabricator via llvm-commits]

fhahn accepted this revision.
fhahn added a comment.

LGTM, thanks!

> I tried to create such a test but it needs to run with scalable vectors, otherwise the code under the check on line 3010 is not exercised. It doesn't seem possible at the moment to test it without having a target (e.g. the cost-model prevents the use of scalable vectors due to Invalid costs, even when using `-force-target-instruction-cost=1`).

Ah right, thanks for checking!



================
Comment at: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp:8749
   VPBasicBlock *EB = TopRegion->getExitingBasicBlock();
-  EB->appendRecipe(CanonicalIVIncrement);
-
-  if (Style == TailFoldingStyle::DataAndControlFlow) {
+  if (Style == TailFoldingStyle::DataAndControlFlow ||
+      Style == TailFoldingStyle::DataAndControlFlowWithoutRuntimeCheck) {
----------------
Is this just `useActiveLaneMaskForControlFlow`?


================
Comment at: llvm/test/Transforms/LoopVectorize/AArch64/sve-low-trip-count.ll:10
+; CHECK:         %[[CMP:.*]] = icmp ugt i64 7, %[[VSCALE_X_VF]]
+; CHECK:         %[[TRIP_COUNT:.*]] = select i1 %[[CMP]], i64 %[[N_MINUS_VF]], i64 0
 ; CHECK:       vector.body:
----------------
Might be worth to include the `%` in the pattern, like the other variables in this file do?


================
Comment at: llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll:26
+; VPLANS-NEXT:     WIDEN store ir<%gep>, ir<%val>, vp<%6>
+; VPLANS-NEXT:     EMIT vp<%9> = VF * Part +  vp<%5>
+; VPLANS-NEXT:     EMIT vp<%10> = active lane mask vp<%9> vp<%3>
----------------
It would be great if you could update the test here to use named variables for the the value numbers here, to avoid having to update every check line if the numbering changes slightly.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D142109