[llvm] 9dd1168 - [docs] Speculative link syntax fix

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-02-13T09:42:35-08:00
New Revision: 9dd1168fe115f6a00d337deaf98bbb396cd6cd43

URL: https://github.com/llvm/llvm-project/commit/9dd1168fe115f6a00d337deaf98bbb396cd6cd43
DIFF: https://github.com/llvm/llvm-project/commit/9dd1168fe115f6a00d337deaf98bbb396cd6cd43.diff

LOG: [docs] Speculative link syntax fix

Added: 
    

Modified: 
    llvm/docs/RISCVUsage.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index a24246dbf1dd..5fd4fb350189 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -73,8 +73,8 @@ on support follow.
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
-     ``Zicsr``        (`See Note <#riscv-i2p1_note>`__)
-     ``Zifencei``     (`See Note <#riscv-i2p1_note>`__)
+     ``Zicsr``        (`See Note <#riscv-i2p1-note>`__)
+     ``Zifencei``     (`See Note <#riscv-i2p1-note>`__)
      ``Zihintpause``  Assembly Support
      ``Zkn``          Supported
      ``Zknd``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
@@ -127,7 +127,7 @@ Supported
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
 
-.. _riscv-i2p1_note:
+.. _riscv-i2p1-note:
 
 ``zicsr``, ``zifencei``
   Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of new extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification document.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA, but attempts to explicitly enable the extensions will error.