[llvm] 0c412fe - [RISCV][docs] Describe status of zicsr and zifencei

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-02-13T09:08:27-08:00
New Revision: 0c412fed360f491e2c33373ffae12e10574a2f0e

URL: https://github.com/llvm/llvm-project/commit/0c412fed360f491e2c33373ffae12e10574a2f0e
DIFF: https://github.com/llvm/llvm-project/commit/0c412fed360f491e2c33373ffae12e10574a2f0e.diff

LOG: [RISCV][docs] Describe status of zicsr and zifencei

This has been a repeated point of recent confusion. There are a couple attempts in flight to change the way we handle the extensions, but for the moment, let's just document what's going on.

Differential Revision: https://reviews.llvm.org/D14392

Added: 
    

Modified: 
    llvm/docs/RISCVUsage.rst

Removed: 
    


################################################################################
diff  --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index d9e6fc45e037..a24246dbf1dd 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -73,6 +73,8 @@ on support follow.
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
+     ``Zicsr``        (`See Note <#riscv-i2p1_note>`__)
+     ``Zifencei``     (`See Note <#riscv-i2p1_note>`__)
      ``Zihintpause``  Assembly Support
      ``Zkn``          Supported
      ``Zknd``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
@@ -125,6 +127,11 @@ Supported
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
 
+.. _riscv-i2p1_note:
+
+``zicsr``, ``zifencei``
+  Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of new extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification document.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA, but attempts to explicitly enable the extensions will error.
+
 Experimental Extensions
 =======================