[PATCH] D143924: [RISCV][docs] Describe status of zicsr and zifencei

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 accepted this revision.
jrtc27 added inline comments.


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Comment at: llvm/docs/RISCVUsage.rst:133
+``zicsr``, ``zifencei``
+  Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA, but attempts to explicitly enable the extensions will error.
+
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Minor tweak to make it more obvious


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https://reviews.llvm.org/D143924