[PATCH] D143924: [RISCV][docs] Describe status of zicsr and zifencei

[Philip Reames via Phabricator via llvm-commits]

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This has been a repeated point of recent confusion.  There are a couple attempts in flight to change the way we handle the extensions, but for the moment, let's just document what's going on.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143924

Files:
  llvm/docs/RISCVUsage.rst


Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -73,6 +73,8 @@
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
+     ``Zicsr``        (`See Note <#riscv-i2p1_note>`__)
+     ``Zifencei``     (`See Note <#riscv-i2p1_note>`__)
      ``Zihintpause``  Assembly Support
      ``Zkn``          Supported
      ``Zknd``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
@@ -125,6 +127,11 @@
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
 
+.. _riscv-i2p1_note:
+
+``zicsr``, ``zifencei``
+  Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA, but attempts to explicitly enable the extensions will error.
+
 Experimental Extensions
 =======================
 


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