[PATCH] D141924: [IR] Add new intrinsics interleave and deinterleave vectors

Caroline via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 13 02:46:35 PST 2023


CarolineConcatto added a comment.

Thank you all for the suggestion.
I believe I have addressed all of them.
Carol



================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:11563-11564
+  SmallVector<EVT, 4> OutVTs;
+  ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
+                  OutVTs);
+
----------------
paulwalker-arm wrote:
> Given how the intrinsic is defined, what do you think of using `EVT OutVT = InVec.getValueType().getHalfNumVectorElementsVT();` rather than the more expensive looking call to ComputeValueVTs.
Thank you, I was not aware of this function.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:23580
+                            Op.getOperand(1));
+  return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(OpVT, OpVT), Even,
+                     Odd);
----------------
luke wrote:
> paulwalker-arm wrote:
> > I think `Op->getVTList()` should work here?
> Could you use `DAG.getMergeValues`  here too?
Thank you Luke, also missed that function when looking at MERGE.


Repository:
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  https://reviews.llvm.org/D141924/new/

https://reviews.llvm.org/D141924



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