[PATCH] D143838: [X86] Improve (select carry C1+1 C1)

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:52553
+  }
+
   if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
----------------
This block of code is duplicated in `CombineOr`/`CombineXor`. Maybe add a helper?
```
static SDValue combineOrXorWithSETCC(SDNode *N, SDValue N0, SDValue N1) {
  // Delegate to combineAddOrSubToADCOrSBB if we have:
  //
  //   (xor/or (zero_extend (setcc)) imm)
  //
  // where imm has its LSB set, in which case the XOR is equivalent to SUB
  // with the operands swapped.
  SDLoc DL(N);
  if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
      N0.getOperand(0).getOpcode() == X86ISD::SETCC) {
    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
      bool N1COdd = N1C->getZExtValue() & 1;
      if (N->getOpcode() == ISD::OR ? !N1COdd : N1COdd) {
        if (SDValue R = combineAddOrSubToADCOrSBB(N->getOpcode() == ISD::XOR,
                                                  DL, VT, N1, N0, DAG))
          return R;
      }
    }
  }
}
```


================
Comment at: llvm/test/CodeGen/X86/select_const.ll:548
+
+define i32 @select_carry_7_6(i32 %X) {
+; CHECK-LABEL: select_carry_7_6:
----------------
Two things regarding the tests.

1) there should be some tests for the `sbb` case.
2) can you split this into two patches, one for adding the tests (w.o the code change to isellowering) and another with the isellowering changes so we can see the changes more easily.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143838/new/

https://reviews.llvm.org/D143838