[PATCH] D136529: [DAG] canCreateUndefOrPoison - add support for SRA/SRL shift opcode (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv64zbb.ll:255
 ; RV64I-NEXT:    .cfi_offset ra, -8
-; RV64I-NEXT:    srliw a1, a0, 1
+; RV64I-NEXT:    srli a1, a0, 1
 ; RV64I-NEXT:    or a0, a0, a1
----------------
@craig.topper I'm familiar with the riscv shift code, but moving the freeze out of the way has changed:
```
  t2: i64,ch = CopyFromReg t0, Register:i64 %0
      t127: i64 = and t2, Constant:i64<4294967295>
    t30: i64 = srl t127, Constant:i64<1>
```
to
```
    t2: i64,ch = CopyFromReg t0, Register:i64 %0
  t4: i64 = AssertZext t2, ValueType:ch:i31
    t32: i64 = srl t4, Constant:i64<1>
  t33: i64 = or t4, t32
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136529/new/

https://reviews.llvm.org/D136529