[PATCH] D143796: [SelectionDAG] Negate constant offset before morphing load/store node with pre-dec/post-dec addressing mode.

[Huihui Zhang via Phabricator via llvm-commits]

huihuiz created this revision.
huihuiz added reviewers: efriedma, RKSimon, lebedev.ri, dmgreen.
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huihuiz requested review of this revision.

If the addressing mode for a load/store node is pre/post decrementing, if the
offset is a constant, then we need to negate that constant before passing it to
node morphing.

This is addressing https://github.com/llvm/llvm-project/issues/60645.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143796

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/test/CodeGen/AArch64/pre-dec-addrmode-constant-offset.ll


Index: llvm/test/CodeGen/AArch64/pre-dec-addrmode-constant-offset.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/pre-dec-addrmode-constant-offset.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
+
+; Reduced test from https://github.com/llvm/llvm-project/issues/60645.
+; To check that we are generating -32 as offset for the first pre-dec store.
+
+define i8* @pr60645(i8* %ptr, i64 %t0) {
+; CHECK-LABEL: pr60645:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub x8, x0, x1, lsl #2
+; CHECK-NEXT:    str wzr, [x8, #-32]!
+; CHECK-NEXT:    stur wzr, [x8, #-8]
+; CHECK-NEXT:    ret
+  %t1 = add nuw nsw i64 %t0, 8
+  %t2 = mul i64 %t1, -4
+  %t3 = getelementptr i8, i8* %ptr, i64 %t2
+  %t4 = bitcast i8* %t3 to i32*
+  store i32 0, i32* %t4, align 4
+  %t5 = shl i64 %t1, 2
+  %t6 = sub nuw nsw i64 -8, %t5
+  %t7 = getelementptr i8, i8* %ptr, i64 %t6
+  %t8 = bitcast i8* %t7 to i32*
+  store i32 0, i32* %t8, align 4
+  ret i8* %ptr
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3360,8 +3360,12 @@
       SDValue Imm = RecordedNodes[RecNo].first;
 
       if (Imm->getOpcode() == ISD::Constant) {
-        const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
-        Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch),
+        int64_t Val = cast<ConstantSDNode>(Imm)->getSExtValue();
+        if (auto LSBaseNode = dyn_cast<LSBaseSDNode>(NodeToMatch))
+          if (LSBaseNode->getAddressingMode() == ISD::PRE_DEC ||
+              LSBaseNode->getAddressingMode() == ISD::POST_DEC)
+            Val = -Val;
+        Imm = CurDAG->getTargetConstant(Val, SDLoc(NodeToMatch),
                                         Imm.getValueType());
       } else if (Imm->getOpcode() == ISD::ConstantFP) {
         const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();


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