[PATCH] D143475: [AArch64] Fix creation of invalid instructions with XZR register

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp:326
+      MI.getOperand(1).getReg() == AArch64::WZR)
+    return false;
+
----------------
efriedma wrote:
> Is the transform assuming that the immediate is on the RHS (operand index 2)?  If so, could you update the comment describing the transform to note that explicitly?  Otherwise, it isn't really clear why operand index 1 is special.
Yep that could do with a better comment. Will do, thanks.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143475/new/

https://reviews.llvm.org/D143475