[llvm] 505cf2b - [X86] combineConcatVectorOps - merge 256-bit logic ops on AVX2+
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 6 07:42:11 PST 2023
Author: Simon Pilgrim
Date: 2023-02-06T15:41:58Z
New Revision: 505cf2b6a5f2b5d4aba449172283cbe2776662df
URL: https://github.com/llvm/llvm-project/commit/505cf2b6a5f2b5d4aba449172283cbe2776662df
DIFF: https://github.com/llvm/llvm-project/commit/505cf2b6a5f2b5d4aba449172283cbe2776662df.diff
LOG: [X86] combineConcatVectorOps - merge 256-bit logic ops on AVX2+
AVX1 doesn't benefit as nearly all integer ops will stay as 128-bit ops.
This only exposes a couple of minor changes but will be a lot more useful in an upcoming shuffle combining patch.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vector-fshl-256.ll
llvm/test/CodeGen/X86/vector-fshr-256.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 5331b186504b..90240926d3ae 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -55470,8 +55470,8 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
case ISD::OR:
case ISD::XOR:
case X86ISD::ANDNP:
- // TODO: Add 256-bit support.
- if (!IsSplat && VT.is512BitVector()) {
+ if (!IsSplat && ((VT.is256BitVector() && Subtarget.hasInt256()) ||
+ (VT.is512BitVector() && Subtarget.useAVX512Regs()))) {
MVT SrcVT = Op0.getOperand(0).getSimpleValueType();
SrcVT = MVT::getVectorVT(SrcVT.getScalarType(),
NumOps * SrcVT.getVectorNumElements());
diff --git a/llvm/test/CodeGen/X86/vector-fshl-256.ll b/llvm/test/CodeGen/X86/vector-fshl-256.ll
index 5cc7cd2fc45d..31121f10a83a 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-256.ll
@@ -722,15 +722,15 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm6 = [249,249,249,249,249,249,249,249,249,249,249,249,249,249,249,249]
; XOPAVX2-NEXT: vpaddb %xmm6, %xmm5, %xmm7
; XOPAVX2-NEXT: vpshlb %xmm7, %xmm3, %xmm3
-; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm7
-; XOPAVX2-NEXT: vpshlb %xmm5, %xmm7, %xmm5
-; XOPAVX2-NEXT: vpor %xmm3, %xmm5, %xmm3
; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
; XOPAVX2-NEXT: vpaddb %xmm6, %xmm2, %xmm4
; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
+; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1
+; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
+; XOPAVX2-NEXT: vpshlb %xmm5, %xmm3, %xmm3
; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
ret <32 x i8> %res
@@ -1965,17 +1965,17 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,0,7,6,5,4,3,2,1]
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
-; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm4
-; XOPAVX2-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5
-; XOPAVX2-NEXT: vpshlb %xmm5, %xmm4, %xmm4
-; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm6 = [249,250,251,252,253,254,255,0,249,0,255,254,253,252,251,250]
-; XOPAVX2-NEXT: vpshlb %xmm6, %xmm4, %xmm4
-; XOPAVX2-NEXT: vpor %xmm4, %xmm2, %xmm2
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpshlb %xmm5, %xmm1, %xmm1
-; XOPAVX2-NEXT: vpshlb %xmm6, %xmm1, %xmm1
-; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
+; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
+; XOPAVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
+; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
+; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [249,250,251,252,253,254,255,0,249,0,255,254,253,252,251,250]
+; XOPAVX2-NEXT: vpshlb %xmm4, %xmm2, %xmm2
+; XOPAVX2-NEXT: vpshlb %xmm3, %xmm1, %xmm1
+; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
+; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
+; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <32 x i8> %res
diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll
index 77c228a71b26..08550faa0e97 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll
@@ -749,19 +749,19 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; XOPAVX2-NEXT: vpsubb %xmm3, %xmm4, %xmm5
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm6
; XOPAVX2-NEXT: vpshlb %xmm5, %xmm6, %xmm5
-; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
-; XOPAVX2-NEXT: vpxor %xmm6, %xmm3, %xmm3
-; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm7
-; XOPAVX2-NEXT: vpaddb %xmm7, %xmm7, %xmm7
-; XOPAVX2-NEXT: vpshlb %xmm3, %xmm7, %xmm3
-; XOPAVX2-NEXT: vpor %xmm5, %xmm3, %xmm3
; XOPAVX2-NEXT: vpsubb %xmm2, %xmm4, %xmm4
; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
-; XOPAVX2-NEXT: vpxor %xmm6, %xmm2, %xmm2
+; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm1, %ymm1
+; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
+; XOPAVX2-NEXT: vpxor %xmm4, %xmm3, %xmm3
+; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm5
+; XOPAVX2-NEXT: vpaddb %xmm5, %xmm5, %xmm5
+; XOPAVX2-NEXT: vpshlb %xmm3, %xmm5, %xmm3
+; XOPAVX2-NEXT: vpxor %xmm4, %xmm2, %xmm2
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
+; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
ret <32 x i8> %res
@@ -1769,16 +1769,16 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,255,254,253,252,251,250,249,0,249,250,251,252,253,254,255]
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
-; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm4
-; XOPAVX2-NEXT: vpaddb %xmm4, %xmm4, %xmm4
-; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm5 = [7,6,5,4,3,2,1,0,7,0,1,2,3,4,5,6]
-; XOPAVX2-NEXT: vpshlb %xmm5, %xmm4, %xmm4
-; XOPAVX2-NEXT: vpor %xmm2, %xmm4, %xmm2
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm1, %xmm1
+; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
+; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
+; XOPAVX2-NEXT: vpaddb %xmm2, %xmm2, %xmm2
+; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [7,6,5,4,3,2,1,0,7,0,1,2,3,4,5,6]
+; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpshlb %xmm5, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpshlb %xmm3, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
+; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <32 x i8> %res
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