[PATCH] D143394: [RISCV] Add performMULcombine to perform strength-reduction

[Philipp Tomsich via Phabricator via llvm-commits]

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The RISC-V backend thus far does not provide strength-reduction, which
causes a long (but not complete) list of 3-instruction patterns listed
to utilize the shift-and-add instruction from Zba and XTHeadBa in
strength-reduction.

This adds the logic to perform strength-reduction through the DAG
combine for ISD::MUL.  Initially, we wire this up for XTheadBa only,
until this has had some time to settle and get real-world test
exposure.

The following strength-reductions strategies are currently supported:

- XTheadBa
  - C = (n + 1)           // th.addsl
  - C = (n + 1)k          // th.addsl, slli
  - C = (n + 1)(m + 1)    // th.addsl, th.addsl
  - C = (n + 1)(m + 1)k   // th.addsl, th.addsl, slli
  - C = ((n + 1)m + 1)    // th.addsl, th.addsl
  - C = ((n + 1)m + 1)k   // th.addslm th.addsl, slli
- base ISA
  - C being 2 set-bits    // slli, slli, add

  			       (possibly slli, th.addsl)

Even though the slli+slli+add sequence would we supported without
XTheadBa, this currently is gated to avoid having to update a large
number of test cases (i.e., anything that has a multiplication with a
constant where only 2 bits are set) in this commit.

With the strength reduction now being performed in performMUL combine,
we drop the (now redundant) patterns from RISCVInstrInfoXTHead.td.

Depends on D143029 <https://reviews.llvm.org/D143029>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D143394

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

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