[PATCH] D140952: Teach the AArch64 backend to materialize immediates using a pair of ORR-immediateinstructions.

Mon Feb 6 00:52:47 PST 2023

dmgreen added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp:169
+    case AArch64::ANDXri:
+      if (I->Op1 == 0) {
+        MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
----------------
resistor wrote:
> dmgreen wrote:
> > resistor wrote:
> > > dmgreen wrote:
> > > > Can this happen?
> > > I'm not aware that anything creates it today, but I thought it was better to have the API of be orthogonal, so as to minimize surprise for any future folks touching this area.
> > An AND of 0 would just be a way of creating 0, and an AND would be a strange way of creating it. The Or with a WZR is the canonical form of a mov, but the And sounds like it would make less sense and might be a bug if it did come up. Perhaps change it to an assert that `I->Op1 != 0` instead.
> That's not what's happening here. The 0 isn't in the immediate operand, but in the register number. It's a signaling mechanism that is used to tell the AArch64ExpandPseudos pass what to do.
But XZR is zero, so this is doing `0 & imm`, which is always zero. So the result will always just be an awkward way of writing `movi 0`. It's not a big deal either way, but if we want a zero we should be using the more canonical `ORRWrs` that processors will recognize and optimize for.  But if anything gets here it is likely a bug in AArch64_IMM::expandMOVImm.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140952/new/

https://reviews.llvm.org/D140952