[PATCH] D142594: [AArch64] Eliminating the use of integer unit in moving from a Neon scalar result of a uaddlv to a Neon vector

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Tablegen patterns are always an option - there is no problem with adding those. Like you say the lowering of ADDV reductions is a little odd in places. If you wanted to fix this very generically it could be written as a post-isel peephole optimization, perhaps in AArch64MIPeepholeOpt. I've not looked deeply into the issues, but It could transform `fmov	w8, s1; mov.s	v2[0], w8` to an lane move instruction, which replaces two fairly slow instructions with a fast one. Happening later it might help in more cases than just the reductions.


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https://reviews.llvm.org/D142594